MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 11

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MPC8533EVTARJA

Manufacturer Part Number
MPC8533EVTARJA
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTARJA

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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2.4.5
The MPC8533E supports DDR and DDR2 SDRAM. The memory interface controls main memory
accesses and provides for a maximum of 16 Gbytes of main memory.
The MPC8533E supports a variety of SDRAM configurations. SDRAM banks can be built using DIMMs
or directly-attached memory devices. Sixteen multiplexed address signals provide for device densities of
from 64 Mbits to 4 Gbits. Four chip select signals support up to four banks of memory. The MPC8533E
supports bank sizes from 64 Mbytes to 4 Gbytes. Nine column address strobes (MDM[0:8]) are used to
provide byte selection for memory bank writes.
The MPC8533E can be configured to retain the currently active SDRAM page for pipelined burst accesses.
Page mode support of up to 16 simultaneously open pages (32 for DDR2) can dramatically reduce access
latencies for page hits. Depending on the memory system design and timing parameters, using page mode
can save 3 to 4 clock cycles from subsequent burst accesses that hit in an active page.
Using ECC, the MPC8533E detects and corrects all single-bit errors and detects all double-bit errors and
all errors within a nibble.
The MPC8533E can invoke a level of system power management by asserting the MCKE SDRAM signal
on-the-fly to put the memory into a low-power sleep mode.
The MPC8533E offers both hardware and software options to support battery-backed main memory. In
addition, the DDR controller offers an initialization bypass feature which system designers may use to
prevent re-initialization of main memory during system power-on following abnormal shutdown.
2.4.6
The MPC8533E supports a 32-bit PCI controller that can operate at speeds of up to 133 MHz. Other
features include:
Freescale Semiconductor
Compatible with PCI Local Bus Specification, Revision 2.2, supporting 32- and 64-bit addressing
Can function as host or agent bridge interface
As a master, supports read and write operations to PCI memory space, PCI I/O space, and PCI
configuration space
Can generate PCI special-cycle and interrupt-acknowledge commands. As a target, it supports read
and write operations to system memory as well as configuration accesses.
Supports PCI-to-memory and memory-to-PCI streaming, memory prefetching of PCI read
accesses, and posting of processor-to-PCI and PCI-to-memory writes
PCI 3.3-V compatible with selectable hardware-enforced coherency
DDR SDRAM Controller
PCI Controller
MPC8533E Integrated Host Processor Product Brief, Rev. 0
Features
11

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