MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 12

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Features
2.4.7
The MPC8533E supports three PCI Express controllers compliant with the PCI Express Base
Specification Revision 1.0a. Power-on reset configuration options allow root complex or endpoint
functionality.
The physical layers of the PCI Express controllers operate at a 2.5-Gbaud data rate (effective rate of 2
Gbps due to encoding overhead) per lane. Receive and transmit ports operate independently, resulting in
an aggregate theoretical bandwidth of 16 Gbps (x4 link).
PCI Express interface features include:
2.4.8
The MPC8533E PIC implements the logic and programming structures of the OpenPIC architecture,
providing for external interrupts (with fully nested interrupt delivery), message interrupts, internal-logic
driven interrupts, and global high-resolution timers. Up to 16 programmable interrupt priority levels are
supported.
The PIC can be bypassed to allow use of an external interrupt controller.
2.4.9
The MPC8533E provides an integrated four-channel DMA controller, which can transfer data between any
of its I/O or memory ports or between two devices or locations on the same port. The DMA controller also
can be used as follows:
There are two I
devices for expansion and system development.
The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550
programming models. Both the transmitter and receiver support 16-byte FIFOs.
The MPC8533E local bus controller (LBC) port allows connections with a wide variety of external
memories, DSPs, and ASICs. Three separate state machines share the same external pins and can be
programmed separately to access different types of devices. The general-purpose chip select machine
(GPCM) controls accesses to asynchronous devices using a simple handshake protocol. The user
programmable machine (UPM) can be programmed to interface to synchronous devices or custom ASIC
interfaces. The SDRAM controller provides access to standard SDRAM. Each chip select can be
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Two x4/x2/x1 interfaces and one x1 interface
Selectable operation as root complex or endpoint
Both 32- and 64-bit addressing and 256-byte maximum payload size
Full 64-bit decode with 36-bit wide windows
To chain (both extended and direct) through local memory-mapped chain descriptors.
To handle misaligned transfers, as well as stride transfers and complex transaction chaining.
To specify local attributes such as snoop and L2 write stashing.
PCI Express Interface
Programmable Interrupt Controller (PIC)
DMA Controller, I
2
C controllers. These synchronous, multimaster buses can be connected to additional
MPC8533E Integrated Host Processor Product Brief, Rev. 0
2
C, DUART, and Local Bus Controller
Freescale Semiconductor