MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 486

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
The AESU is also used for performing the exclusive OR (XOR) operation used to generate parity data for
RAID storage applications. When operating in this mode, no session keys are involved, and the AESU
XORs up to three data streams at a time to produce parity data.
For more information, refer to
12.1.2.7
The KEU is a functional block capable of encrypting/decrypting and/or performing integrity checks on
64-bit blocks of data using a 128-bit key. The KEU is designed to be compatible with both the F8 and F9
algorithms as defined in the ETSI/SAGE specification document 1 for the 3GPP standard. In addition, if
the KEU is supplied with an original MAC value, it is capable of performing a bitwise check of this
original MAC against an F9 MAC generated by the KEU.
The KEU also performs Kasumi-based algorithms that are used to protect data in 2G and 2.5G protocols,
specifically A5/3 for GSM and EDGE, and GEA-3 for GPRS.
For more information, refer to
12.1.3
The SEC includes four crypto-channels that manage data and EU function. Each channel contains the
following:
Whenever a crypto-channel is idle and its fetch FIFO is non-empty, the channel reads the next descriptor
pointer from the fetch FIFO. Using this pointer, the channel fetches the descriptor and places it in its
descriptor buffer. To service this descriptor, the channel directs execution of the following steps:
12-8
•
•
•
•
•
•
1. Analyze the descriptor header to determine the cryptographic services required, and request use of
2. Wait for the controller to grant access to the required EUs.
3. Set the appropriate mode bits in the EU(s) for the required service.
4. Fetch data parcels using pointers from the descriptor buffer, and place them in either an EU input
5. If the data size is greater than EU FIFO size, continue fetching input data, and writing output data
6. Wait for EU(s) to complete processing.
A fetch FIFO, which holds a queue of pointers to descriptors waiting to be serviced
A configuration register, which allows the user a number of options for SEC event signaling
Control registers containing information about the transaction in process
A status register containing an indication of the last unfulfilled bus request
A descriptor buffer memory used to store the active descriptor
Scatter and gather link table buffer memory used to store the active link table
the appropriate EUs from the controller.
FIFO or EU registers (as appropriate). The term data parcel refers here to any input or output of a
cryptographic process, such as a key, hash result, input context, output context, or text-data.
Context refers to either an initialization vector (IV) or other internal EU state that can be read out
or loaded in. Text-data refers to plaintext or ciphertext to be operated on.
to memory.
Crypto-Channels
Kasumi Execution Unit (KEU)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Section 12.4.6, “Advanced Encryption Standard Execution Unit (AESU).”
Section 12.4.7, “Kasumi Execution Unit (KEU).”
Freescale Semiconductor