MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 970

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DMA Controller
16.4.4
The DMA engine recognizes list descriptors and link descriptors. List descriptors connect lists of link
descriptors. Link descriptors describe the DMA activity that is to take place. DMA descriptors are built in
either local or remote memory and are connected by the next descriptor fields. Only link descriptors
contain information for the DMA controller to transfer data. Software must ensure that each descriptor is
32-byte aligned. The last link descriptor in the last list in memory sets the NLNDARn[EOLND] bit in the
next link descriptor; and NLSDARn[EOLSD] in the next list descriptor fields indicating that these are the
last descriptors in memory. Software initializes the current list descriptor address register to point to the
first list descriptor in memory. The DMA controller traverses through the descriptor lists until the last link
descriptor is met. For each link descriptor in the chain, the DMA controller starts a new DMA transfer with
the control parameters specified by that descriptor. Link and list descriptor fetches always snoop the local
memory space.
Table 16-22
16-34
Next list descriptor
extended address
Next list descriptor
address
First link descriptor
extended address
First link descriptor
address
Source stride
Destination stride
Descriptor Field
DMA Descriptors
summarizes the DMA list descriptors.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Software must ensure that each descriptor is aligned on a 32-byte boundary.
Points to the next list descriptor in memory. After the DMA controller reads the descriptor from memory,
this field is loaded into the next list descriptor extended address registers.
Points to the next list descriptor in memory. After the DMA controller reads the descriptor from memory,
this field is loaded into the next list descriptor address registers.
Points to the first link descriptor in memory for this list. After the DMA controller reads the descriptor from
memory, this field is loaded into the current link descriptor extended address registers.
Points to the first link descriptor in memory for this list. After the DMA controller reads the descriptor from
memory, this field is loaded into the current link descriptor address registers.
Contains the stride information used for the data source if striding is enabled for a link in the list
Contains the stride information used for the data destination if striding is enabled for a link in the list
Table 16-22. List DMA Descriptor Summary
NOTE
Description
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