73M1866B-IMR/F Maxim Integrated Products, 73M1866B-IMR/F Datasheet - Page 40

• Manufacturer Part Number: 73M1866B-IMR/F
• Description: MICRODAA SGL PCM HIGHWAY 42-QFN
• Manufacturer: Maxim Integrated Products
• Series: MicroDAA™r

Specifications of 73M1866B-IMR/F

• Includes: PCM Highway
• Function: Data Access Arrangement (DAA)
• Interface: PCM, Serial, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 42-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Power (watts): -

73M1866B/73M1966B Data Sheet
6.1
The Register Map as read from a 73M1x66B Host-Side Device consists of two groups. The first is the
Host-Side Device registers (0x00 through 0x10 and 0x20 through 0x24) and the second is a copy of the
Line-Side Device registers (0x12 through 0x1F).
As an extra degree of integrity, the 73M1x66B supports the ability to manually monitor the registers of its
Line-Side Device. This is achieved by using the Manual Poll Function. The Line-Side registers that can
be polled are 0x12 through 0x18 (index values 0x0-0x6 respectively).
The method is to write the offset address of the Line-Side Device register to be read into the INDX field.
The value of this is the offset index from 0x12; that is, Register 0x12 is 0x0, 0x13 is 0x1, etc. The next
step is to set the POLL bit, which causes the device to read the requested register from the Line-Side
Device. The value of the requested Line-Side Device register is written by the Line-Side Device into
POLVAL (0x1F). This value is compared with that of the Host-Side copy and, if they are the same, the
MATCH bit is set to 1.
The values presented at MATCH and POLVAL are valid approximately 600 μs after a poll request, and
are valid only after the POLL bit has been reset by the Host-Side Device.
40
Function
Mnemonic
INDX
MATCH
POLL
POLVAL
• Read/Write (W) registers change in response to an SPI write transaction and report their correct
• Read Only (R) registers do not change in response to an SPI write transaction but report their
• Write Only (WO) registers are shadow registers to corresponding registers on the Line-Side
While all registers may be read or written to via an SPI operation without error, some registers react
differently to read and write operations, as follows:
Line-Side Device Register Polling
current value for a read SPI transaction.
correct current value for a read SPI transaction.
Device (0x12-0x18) that are written to during the barrier communications, and so are written to
indirectly. The true contents of these Line-Side registers cannot be read directly from the shadow
registers representing them, but these Line-Side registers can be read using the polling register
described in 6.1. Certain events, such as lightning or voltage surges, could corrupt the contents
of the Line-Side registers, so to verify their contents, the polling registers (0x19 and 0x1F) must
be used.
0x19[3:0]
0x19[6]
0x19[7]
0x1F[7:0]
Location
Register
Type
W
W
R
R
Index
Address of the register to be manually polled with the results placed in
POLVAL. This address should be cleared after the poll. Default = 0.
Polling Match
0 = No match. (Default)
1 = This read-only bit indicates that there is match with the
corresponding polled register in the Host-Side Device. The result of
the polling function can be read only after the POLL bit is reset to zero
by the 73M1x66B.
Polling Enable
0 = Polling disabled. (Default)
1 = Manually polls the control register in the Line-Side Device whose
address is given by INDX. The Poll bit remains high until the MATCH
result is available at which time it will be reset to 0 and the MATCH bit
status can be read.
Polling Value
When 73M1x66B is polled, the content of the Line-Side Device
Register given by the offset address in INDX is placed in this register.
Default = 0. This register can be read after the POLL bit has been
reset to zero, indicating the result is ready.
Description
DS_1x66B_001
Rev. 1.6