73M1866B-IMR/F Maxim Integrated Products, 73M1866B-IMR/F Datasheet - Page 42

• Manufacturer Part Number: 73M1866B-IMR/F
• Description: MICRODAA SGL PCM HIGHWAY 42-QFN
• Manufacturer: Maxim Integrated Products
• Series: MicroDAA™r

Specifications of 73M1866B-IMR/F

• Includes: PCM Highway
• Function: Data Access Arrangement (DAA)
• Interface: PCM, Serial, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 42-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Power (watts): -

73M1866B/73M1966B Data Sheet
7.3
The 73M1x66B supports three modes of power control for the device.
In all reduced power modes of operation the SPI interface remains active.
7.4
42
Function
Mnemonic
ENFEH
PWDN
SLEEP
Function
Mnemonic
FRCVCO
LOKDET
Power Management
Device Clock Management
Normal mode
ENFEH = 0
Sleep mode
Power Down
0x0F[7]
0x0F[6]
0x0F[5]
Location
Register
Register
Location
0x0E[7]
0x0D[7]
The 73M1x66B operates normally.
In this mode the Host Side of the Barrier interface is disabled and the
line side device is disabled. The Host side continues to operate
normally.
The device PLL is turned off and PCLK is propagated on the clock
tree. The PCM DX and TSC outputs are tri-stated. Control and status
registers of the Host side maintain their content.
The device is shut down altogether. The registers remain accessible
through the SPI. Control and status registers of the Host side maintain
their content. To restart the PCM operations, the PCODE register
must be set for the appropriate PCLK frequency value.
Type
Type
W
W
W
W
R
Enable Front End Host
1 = Enable Front End of the 73M1906B Host-Side Device. (Default)
0 = Disable Front End of the 73M1906B Host-Side Device.
Power Down Mode
0 = Disable Power Down Mode. (Default)
1 = Enable Power Down Mode.
Sleep Mode
0 = Disable Sleep Mode. (Default)
1 = Enable Sleep Mode.
Force VCO
0 = The system clock is the same as PCLK. (Default)
1 = The system clock is derived from locked PLL. This is set to 0
upon reset, Sleep or Power Down mode enabled.
Phase Locked Loop Lock Detect
0 = PLL is not locked. (Default)
1 = PLL is locked to PCLK.
Description
Description
DS_1x66B_001
Rev. 1.6