JS28F256P30TFA NUMONYX, JS28F256P30TFA Datasheet - Page 34
![IC FLASH 256MBIT 110NS 56TSOP](/photos/7/29/72921/js28f256p30tf_902052_sml.jpg)
JS28F256P30TFA
Manufacturer Part Number
JS28F256P30TFA
Description
IC FLASH 256MBIT 110NS 56TSOP
Manufacturer
NUMONYX
Series
Axcell™r
Datasheet
1.PF48F4000P0ZBQEF.pdf
(94 pages)
Specifications of JS28F256P30TFA
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
256M (16Mx16)
Speed
110ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
56-TSOP
Package
56TSOP
Cell Type
NOR
Density
256 Mb
Architecture
Sectored
Block Organization
Asymmetrical
Location Of Boot Block
Top
Typical Operating Supply Voltage
1.8 V
Sector Size
32KByte x 4|128KByte x 255
Timing Type
Asynchronous|Synchronous
Interface Type
Parallel|Serial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
902052
902052
JS28F256P30TF 902052
902052
JS28F256P30TF 902052
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
JS28F256P30TFA
Manufacturer:
MICRON
Quantity:
946
Part Number:
JS28F256P30TFA
Manufacturer:
MICRON/镁光
Quantity:
20 000
9.3
9.4
9.5
Datasheet
34
The status register can be examined for Blank Check progress and errors by reading
any address within the block being accessed. During a blank check operation, the
Status Register indicates a busy status (SR.7 = 0). Upon completion, the Status
Register indicates a ready status (SR.7 = 1). The Status Register should be checked for
any errors, and then cleared. If the Blank Check operation fails, which means the block
is not completely erased,
OE# toggle (during polling) updates the Status Register.
After examining the Status Register, it should be cleared by the Clear Status Register
command before issuing a new command. The device remains in Status Register Mode
until another command is written to the device. Any command can follow once the
Blank Check command is complete.
Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation.
This allows data to be accessed from memory locations other than the one being
erased. The Erase Suspend command can be issued to any device address. A block
erase operation can be suspended to perform a word or buffer program operation, or a
read operation within any block except the block that is erase suspended (see
Figure 40, “Erase Suspend/Resume Flowchart” on page
When a block erase operation is executing, issuing the Erase Suspend command
requests the WSM to suspend the erase algorithm at predetermined points. The device
continues to output Status Register data after the Erase Suspend command is issued.
Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is
specified in
To read data from the device (other than an erase-suspended block), the Read Array
command must be issued. During Erase Suspend, a Program command can be issued
to any block other than the erase-suspended block. Block erase cannot resume until
program operations initiated during erase suspend complete. Read Array, Read Status
Register, Read Device Identifier, Read CFI, and Erase Resume are valid commands
during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend,
Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase
Suspend.
During an erase suspend, deasserting CE# places the device in standby, reducing
active current. V
while in erase suspend. If RST# is asserted, the device is reset.
Erase Resume
The Erase Resume command instructs the device to continue erasing, and
automatically clears status register bits SR[7,6]. This command can be written to any
address. If status register error bits are set, the Status Register should be cleared
before issuing the next instruction. RST# must remain deasserted (see
“Erase Suspend/Resume Flowchart” on page
Erase Protection
When V
V
error.
PP
is at or below V
PP
= V
Section 16.0, “Program and Erase Characteristics” on page
IL
, absolute hardware erase protection is provided for all device blocks. If
PP
must remain at a valid level, and WP# must remain unchanged
PPLK
, erase operations halt and SR.3 is set indicating a V
the Status Register bit SR.5 will be set (“1”). CE# or
83).
83).
Order Number: 320002-10
63.
Figure 40,
PP
-level
P30-65nm
Mar 2010