PC28F256J3F95A NUMONYX, PC28F256J3F95A Datasheet - Page 14

• Manufacturer Part Number: PC28F256J3F95A
• Description: IC FLASH 256MBIT 95NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F256J3F95A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256M (32M x8, 16M x16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Address Bus: 25/24Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 32M/16M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 898244; 898244; PC28F256J3F95 898244

4.0
Table 4:
Datasheet
14
A[MAX:1]
DQ[15:8]
GND/VSS
DQ[7:0]
Symbol
CE[2:0]
BYTE#
VCCQ
VPEN
WE#
OE#
RP#
STS
VCC
RFU
NC
A0
TSOP & Easy BGA Signal Descriptions
Open Drain
Output
Output
Output
Supply
Signal Descriptions
Table 4
Input/
Input/
Power
Power
Type
Input
Input
Input
Input
Input
Input
Input
Input
—
—
lists the active signals used on J3-65nm and provides a description of each.
BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This
address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is
turned off when BYTE# is high).
ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are
internally latched during a program cycle:
256-Mbit — A[24:1]
LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands
during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read mode. Data
is internally latched during write operations.
HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations.
Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register
reads. Data is internally latched during write operations in x16 mode. DQ[15:8] float in x8 mode
CHIP ENABLE: Activate the 256-Mbit devices’ control logic, input buffers, decoders, and sense
amplifiers. When the device is de-selected (see
256-Mb” on page 15
All timing specifications are the same for these three signals. Device selection occurs with the
falling edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the rising
edge of CE0, CE1, or CE2 that disables the device (see
for 256-Mb” on page 15
RESET: RP#-low resets internal automation and puts the device in power-down mode. RP#-high
enables normal operation. Exit from reset sets the device to read array mode. When driven low,
RP# inhibits write operations which provides data protection during power transitions.
OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.
OE# is active low.
WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active low.
Addresses and data are latched on the rising edge of WE#.
STATUS: Indicates the status of the internal state machine. When configured in level mode
(default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to
indicate program and/or erase completion. For alternate configurations of the Status signal, see the
Configurations command and
tied to VCCQ with a pull-up resistor.
BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on DQ[7:0], while
DQ[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-high
places the device in x16 mode, and turns off the A0 input buffer. Address A1 becomes the lowest-
order address bit.
ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or
configuring lock-bits.
With V
CORE Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when V
≤ V
Caution: Device operation at invalid Vcc voltages should not be attempted.
I/O Power Supply: Power supply for Input/Output buffers.This ball can be tied directly to V
GROUND: Ground reference for device logic voltages. Connect to system ground.
No Connect: Lead is not internally connected; it may be driven or floated.
Reserved for Future Use: Balls designated as RFU are reserved by Numonyx for future device
functionality and enhancement.
LKO
.
PEN
≤ V
PENLK
, memory contents cannot be altered.
), power reduces to standby levels.
Section 11.2, “Status Signal” on page 31
).
Numonyx™ StrataFlash
Name and Function
Table 6, “Chip Enable Truth Table for
Table 6, “Chip Enable Truth Table
®
Embedded Memory (J3-65nm)
. STS is to be
December 2008
319942-02
CC
.
CC