PC28F256J3F95A NUMONYX, PC28F256J3F95A Datasheet - Page 6

• Manufacturer Part Number: PC28F256J3F95A
• Description: IC FLASH 256MBIT 95NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F256J3F95A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256M (32M x8, 16M x16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Address Bus: 25/24Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 32M/16M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 898244; 898244; PC28F256J3F95 898244

Datasheet
6
A Command User Interface (CUI) serves as the interface between the system processor
and internal operation of the device. A valid command sequence written to the CUI
initiates device automation. An internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for block erase, program, and lock-bit
configuration operations.
A block erase operation erases one of the device’s 128-Kbyte blocks typically within one
second, independent of other blocks. Each block can be independently erased 100,000
times. Block erase suspend mode allows system software to suspend block erase to
read or program data from any other block. Similarly, program suspend allows system
software to suspend programming (byte/word program and write-to-buffer operations)
to read data or execute code from any other block that is not being suspended.
Each device incorporates a Write Buffer of 512 words to allow optimum programming
performance. By using the Write Buffer data is programmed more efficiently in buffer
increments.
Memory Blocks are selectively and individually lockable in-system. Individual block
locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase
and program operations. Lock-bit configuration operations set and clear lock-bits (using
the Set Block Lock-Bit and Clear Block Lock-Bits commands).
The Status Register indicates when the WSM’s block erase, program, or lock-bit
configuration operation completes.
The STS (status) output gives an additional indicator of WSM activity by providing both
a hardware signal of status (versus software polling) and status masking (interrupt
masking for background block erase, for example). Status indication using STS
minimizes both CPU overhead and system power consumption. When configured in
level mode (default mode), it acts as a RY/BY# signal. When low, STS indicates that the
WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates
that the WSM is ready for a new command, block erase is suspended (and
programming is inactive), program is suspended, or the device is in reset/power-down
mode. Additionally, the configuration command allows the STS signal to be configured
to pulse on completion of programming and/or block erases.
Three CE signals are used to enable and disable the device. A unique CE logic design (
see
typically required for multi-chip designs. External logic is not required when designing a
single chip, a dual chip, or a 4-chip miniature card or SIMM module.
The BYTE# signal allows either x8 or x16 read/writes to the device:
When the device is disabled (see
page
at V
provides write protection during reset. A reset time (t
high until data outputs are valid. Likewise, the device has a wake time (t
RP#-high until writes to the CUI are recognized. With RP# at V
the Status Register is cleared.
• BYTE#-low enables 8-bit mode; address A0 selects between the low byte and high
• BYTE#-high enables 16-bit operation; address A1 becomes the lowest order
byte.
address and address A0 is not used (don’t care).
IL
Table 6, “Chip Enable Truth Table for 256-Mb” on page
15), with CEx at V
, a further power-down mode is enabled which minimizes power consumption and
IH
and RP# at V
Table 6, “Chip Enable Truth Table for 256-Mb” on
Numonyx™ StrataFlash
IH
, the standby mode is enabled. When RP# is
PHQV
) is required from RP# going
®
15) reduces decoder logic
Embedded Memory (J3-65nm)
IL
, the WSM is reset and
PHWL
December 2008
) from
319942-02