RC28F256P33BFA NUMONYX, RC28F256P33BFA Datasheet - Page 15
![IC FLASH 256MBIT 95NS 64EZBGA](/photos/7/31/73127/rc28f256p33bf_898897_sml.jpg)
RC28F256P33BFA
Manufacturer Part Number
RC28F256P33BFA
Description
IC FLASH 256MBIT 95NS 64EZBGA
Manufacturer
NUMONYX
Series
Axcell™r
Specifications of RC28F256P33BFA
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
256M (16Mx16)
Speed
95ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
64-EZBGA
Cell Type
NOR
Density
256Mb
Interface Type
Parallel/Serial
Boot Type
Bottom
Address Bus
25b
Operating Supply Voltage (typ)
2.5/3/3.3V
Operating Temp Range
-40C to 85C
Package Type
EZBGA
Sync/async
Async/Sync
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
3.6V
Word Size
16b
Number Of Words
32M
Supply Current
50mA
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
898897
898897
RC28F256P33BF 898897
898897
RC28F256P33BF 898897
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
RC28F256P33BFA
Manufacturer:
Micron Technology Inc
Quantity:
10 000
P33-65nm
5.0
Table 5:
5.1
5.2
Note:
5.3
Datasheet
15
Read
Write
Output Disable
Standby
Reset
Notes:
1.
2.
3.
Bus Operation
Asynchronous
Synchronous
Refer to the
operation.
X = Don’t Care (H or L).
RST# must be at V
Bus Operations Summary
Bus Operations
CE# low and RST# high enable device read operations. The device internally decodes
upper address inputs to determine the accessed block. ADV# low opens the internal
address latches. OE# low activates the outputs and gates selected data onto the I/O
bus.
In asynchronous mode, the address is latched when ADV# goes high or continuously
flows through if ADV# is held low. In synchronous mode, the address is latched by the
first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE#
and RST# must be V
Bus cycles to/from the P33-65nm device conform to standard microprocessor bus
operations.
logic levels that must be applied to the device control signal inputs.
Read
To perform a read operation, RST# and WE# must be deasserted while CE# and OE#
are asserted. CE# is the device-select control. When asserted, it enables the flash
memory device. OE# is the data-output control. When asserted, the addressed flash
memory data is driven onto the I/O bus.
Write
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge
of WE# or CE#, whichever occurs first.
shows the bus cycle sequence for each of the supported device commands, while
Table 6, “Command Codes and Definitions” on page 17
Section 15.0, “AC Characteristics” on page 48
Write operations with invalid VCC and/or VPP voltages can produce spurious results and
should not be attempted.
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-
impedance (High-Z) state, WAIT is also placed in High-Z.
Table 7, “Command Bus Cycles” on page 19
RST#
SS
V
V
V
V
V
V
IH
IH
IH
IH
IH
IL
± 0.2 V to meet the maximum specified power-down current.
Table 5, “Bus Operations
Running
CLK
X
X
X
X
X
IH
; CE# must be V
ADV#
X
X
X
L
L
L
CE#
H
X
L
L
L
L
Summary”summarizes the bus operations and the
IL
Table 7, “Command Bus Cycles” on page 19
).
OE#
H
H
X
X
L
L
for signal-timing details.
for valid DQ[15:0] during a write
WE#
H
H
H
X
X
L
describes each command. See
Deasserted
High-Z
High-Z
High-Z
High-Z
WAIT
Driven
Order Number:320003-09
DQ[15:0]
Output
Output
High-Z
High-Z
High-Z
Input
Mar 2010
Notes
2,3
1
2
2