ZL2105ALNF Intersil, ZL2105ALNF Datasheet - Page 23

• Manufacturer Part Number: ZL2105ALNF
• Description: IC DGTL DC-DC CTRLR 3A 36QFN
• Manufacturer: Intersil
• Type: Step-Down (Buck), PWM - Voltage Moder

Specifications of ZL2105ALNF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.6 V ~ 5.5 V
• Current - Output: 3A
• Frequency - Switching: 200kHz ~ 2MHz
• Voltage - Input: 4.5 V ~ 14 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In the ZL2105, the compensation zeros are set by
configuring the FC pin or via the I
once the user has calculated the required settings. This
method eliminates the inaccuracies due to the
component tolerances associated with using external
resistors and capacitors required with traditional analog
controllers. Utilizing the loop compensation settings
shown in Table 19 will yield a conservative crossover
frequency at a fixed fraction of the switching
frequency (f
Step 1:
resonant frequency of the LC filter, f
Step 2:
Step 3:
resistor, R
The FC pin can be pin-strapped as LOW, OPEN, or
HIGH. These three positions are the same as the first
three entries in Table 19.
NLR
Off
On
Table 19. Resistor Settings for Loop Compensation
Calculate the ESR zero frequency (f
Based on Table 19, determine the appropriate
Using the following equation, calculate the
FC
.
S
/20) and 60° of phase margin.
f
23
f
n
zesr
2
f
f
π
f
sw
f
sw
f
sw
f
sw
2
sw
sw
/240 < f
/240 < f
πCRc
/120 < f
/120 < f
1
/60 < f
/60 < f
L
1
f
n
C
Range
2
C/SMBus interface
n
n
n
n
n
n
n
< f
< f
< f
< f
.
< f
< f
sw
sw
sw
sw
sw
sw
/30
/120
/30
/120
/60
/60
ZESR
).
ZL2105
The loop compensation coefficients can also be set via
the I
Note AN2013 for further details. Refer to Application
Note AN2016 for further technical details on setting
loop compensation.
5.12 Non-linear Response (NLR) Settings
The ZL2105 incorporates a non-linear response (NLR)
loop that decreases the response time and the output
voltage deviation in the event of a sudden output load
current step. The NLR loop incorporates a secondary
error signal processing path that bypasses the primary
error loop when the output begins to transition outside
of the standard regulation limits. This scheme results in
a higher equivalent loop bandwidth than what is
possible using a traditional linear loop.
When a load current step function imposed on the
output causes the output voltage to drop below the
lower regulation limit, the NLR circuitry will force a
positive correction signal that will turn on the upper
MOSFET and quickly force the output to increase.
Conversely, a negative load step (i.e. removing a large
load current) will cause the NLR circuitry to force a
negative correction signal that will turn on the lower
MOSFET and quickly force the output to decrease.
2
C/SMBus interface. Please refer to Application
f
f
f
f
f
f
f
f
f
f
f
f
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
/10 > f
/30 > f
/10 > f
/30 > f
/10 > f
/30 > f
/10 > f
/30 > f
/10 > f
/30 > f
/10 > f
/30 > f
f
f
f
f
f
f
f
zesr
zesr
zesr
zesr
zesr
zesr
zesr
> f
> f
> f
> f
> f
> f
Range
zesr
zesr
zesr
zesr
zesr
zesr
zesr
zesr
zesr
zesr
zesr
zesr
sw
sw
sw
sw
sw
sw
> f
> f
> f
> f
> f
> f
> f
> f
> f
> f
> f
> f
/10
/10
/10
/10
/10
/10
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
/30
/60
/30
/60
/30
/60
/30
/60
/30
/60
/30
/60
March 30, 2011
FN6851.2
12.1 k
13.3 k
14.7 k
16.2 k
17.8 k
19.6 k
21.5 k
23.7 k
26.1 k
28.7 k
31.6 k
34.8 k
38.3 k
42.2 k
46.4 k
51.1 k
10 k
11 k
R
FC