CP2110EK Silicon Laboratories Inc, CP2110EK Datasheet - Page 16

• Manufacturer Part Number: CP2110EK
• Description: KIT EVAL FOR CP2110
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2110EK

• Main Purpose: Interface, USB 2.0 to UART (RS485) Bridge
• Embedded: No
• Utilized Ic / Part: CP2110
• Primary Attributes: Full Speed (12Mbps)
• Secondary Attributes: LED Status Indicators
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V
• Product: Interface Development Tools
• For Use With/related Products: CP2110
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-2003

CP2110
7.1. GPIO.0—Clock Output
GPIO.0 is configurable to output a configurable CMOS clock output. The clock output appears at the pin at the
same time the device completes enumeration and exits USB Suspend mode. The clock output is removed from the
pin when the device enters USB Suspend mode. The output frequency is configurable through the use of a divider
and the accuracy is specified in Table 6. When the divider is set to 0, the output frequency is 24 MHz. For divider
values between 1 and 255, the output frequency is determined by the formula:
This divider is independent from the divider used to set UART baud rate.
7.2. GPIO.1-2—Hardware Flow Control (RTS and CTS)
By default, GPIO.1 and GPIO.2 are configured to operate as the hardware flow control pins RTS and CTS. In
addition to the GPIO PROM configuration, the device must be configured to use hardware flow control to use these
pins.
RTS, or Ready To Send, is an active-low output from the CP2110 and indicates to the external UART device that
the CP2110’s UART RX FIFO has not reached the watermark level of 450 bytes and is ready to accept more data.
When the amount of data in the RX FIFO reaches the watermark, the CP2110 pulls RTS high to indicate to the
external UART device to stop sending data.
CTS, or Clear To Send, is an active-low input to the CP2110 and is used by the external UART device to indicate to
the CP2110 when the external UART device’s RX FIFO is getting full. The CP2110 will not send more than two
bytes of data once CTS is pulled high.
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Figure 5. Hardware Flow Control Typical Connection Diagram
CP2110
GPIO.1 – RTS
GPIO.2 – CTS
Equation 4. GPIO.0 Clock Output Frequency
GPIO.0 Clock Frequency
RX
TX
Rev. 1.0
=
----------------------------- -
2 Divider
24 MHz

TX
RX
RTS
CTS
System
RS232