LMK04000BEVAL/NOPB National Semiconductor, LMK04000BEVAL/NOPB Datasheet - Page 12

• Manufacturer Part Number: LMK04000BEVAL/NOPB
• Description: BOARD EVAL PRECISION CLOCK PLL
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LMK04000BEVAL/NOPB

• Main Purpose: Timing, Clock Conditioner
• Embedded: No
• Utilized Ic / Part: LMK04000
• Primary Attributes: 122.88 MHz VCXO
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMK04000BEVAL; LMK04000BEVAL

PLL Loop Filters and Loop Parameters
In jitter cleaning applications that use a cascaded PLL architecture, the first PLL’s purpose is to
substitute the phase noise of a low noise oscillator (VCXO or crystal resonator) for the phase
noise of a “dirty” reference clock. The first PLL is typically configured with a narrow loop
bandwidth in order to minimize the impact of the reference clock phase noise. The reference
clock consequently serves only as a frequency reference rather than a phase reference.
The loop filters on the LMK040xx evaluation board are setup using the approach above. The
loop filter for PLL1 has been configured for a narrow loop bandwidth (< 100 Hz), while the loop
filter of PLL2 has been configured for a wide loop bandwidth (> 100 kHz). The specific loop
bandwidth values depend on the phase noise performance of the oscillator mounted on the board.
The following tables contain the parameters for PLL1 and PLL2 for each oscillator option.
National’s Clock Design Tool can be used to optimize PLL phase noise/jitter for given
specifications. See: http://www.national.com/timing/software/.
PLL 1 Loop Filter
Table 4. PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO and 12.288 MHz Vectron Crystal
Note: PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing
Kφ and N will change the loop bandwidth.
122.88 MHz VCXO option
12.288 MHz Crystal (-XO) option
Loop Filter Components
Loop Filter Components
Loop Bandwidth
Loop Bandwidth
Reference Clock
Reference Clock
Phase Margin
Phase Margin
Frequency
Frequency
L M K 0 4 0 X X - R E V 3
122.88 MHz
C1 = 100 nF
122.88 MHz
C1 = 330 nF
12 Hz
8 Hz
50º
60º
E V A L U A T I O N
Phase Detector Freq
Phase Detector Freq
Kφ (Charge Pump)
Kφ (Charge Pump)
Output Frequency
Output Frequency
12
C2 = 680 nF
C2 = 10 uF
VCO Gain
VCO Gain
B O A R D
O P E R A T I N G
122.88 MHz (To PLL 2)
12.288 MHz (To PLL 2)
I N S T R U C T I O N S
2.5 kHz/Volt
1.5 kHz/Volt
R2 = 3.9 kΩ
R2 = 39 kΩ
1.024 MHz
1.024 MHz
100 uA
100 uA