ISLA112P50IR72EV1Z Intersil, ISLA112P50IR72EV1Z Datasheet - Page 29

• Manufacturer Part Number: ISLA112P50IR72EV1Z
• Description: EVAL BOARD FOR ISLA112P50IR73
• Manufacturer: Intersil

Specifications of ISLA112P50IR72EV1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADDR
(Hex)
56-5F
65-6F
76-BF
55
60
61
62
63
64
70
71
72
73
74
75
output_mode_A
output_mode_B
Fine Offset Init
PARAMETER
Coarse Offset
Fine Gain Init
config_status
Medium Gain
Sample Time
I2E AC RMS
phase_slip
Hysteresis
Skew Init
skew_diff
Reserved
reserved
reserved
reserved
NAME
Init
Init
29
(MSB)
BIT 7
other codes = reserved
Output Mode [2:0]
000 = Pin Control
001 = LVDS 2mA
010 = LVDS 3mA
100 = LVCMOS
1 = slow
0 = fast
Range
BIT 6
Result
XOR
DLL
TABLE 15. SPI MEMORY MAP (Continued)
Sample Time Skew Initialization value
Reserved
BIT 5
Coarse Offset Initialization value
Medium Gain Initialization value
Fine Offset Initialization value
Fine Gain Initialization value
ISLA112P50
AC RMS Power Hysteresis
Reserved
Differential Skew
BIT 4
Reserved
Reserved
Reserved
BIT 3
001 = Twos Complement
Other codes = Reserved
BIT 2
Output Format [2:0]
Reserved (must be 0)
100 = Offset Binary
000 = Pin Control
010 = Gray Code
BIT 1
(LSB)
BIT 0
Clock
Edge
Next
Soft Reset
Soft Reset
Read Only
affected
affected
affected
VALUE
(Hex)
Reset
DEF.
NOT
NOT
NOT
Soft
10h
80h
80h
80h
80h
80h
80h
00h
00h
00h
00h
by
by
by
June 17, 2010
INDEXED
/GLOBAL
FN7604.1
G
G
G
G
G
G
G
G
G
G
G
G
G
G