ISLA112P50IR72EV1Z Intersil, ISLA112P50IR72EV1Z Datasheet - Page 30

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ISLA112P50IR72EV1Z

Manufacturer Part Number
ISLA112P50IR72EV1Z
Description
EVAL BOARD FOR ISLA112P50IR73
Manufacturer
Intersil
Datasheets

Specifications of ISLA112P50IR72EV1Z

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Equivalent Circuits
INP
INN
ADDR
(Hex)
C6-FF
C0
C1
C2
C3
C4
C5
AVDD
AVDD
user_patt 1_lsb
user_patt1_msb
user_patt 2_lsb
user_patt2_msb
PARAMETER
FIGURE 46. ANALOG INPUTS
Reserved
500O Ω
reserved
test_io
NAME
Φ
F 1
Φ
F 1
30
User Test Mode
(MSB)
BIT 7
01 = Alternate
10 = Reserved
11 = Reserved
B15
B15
B7
B7
00 = Single
CSAMP
CSAMP
[1:0]
1.6pF
1.6pF
Φ
F 2
Φ
F 2
BIT 6
B14
B14
TABLE 15. SPI MEMORY MAP (Continued)
B6
B6
Φ
F 3
Φ
F 3
BIT 5
PIPELINE
PIPELINE
B13
B13
CHARGE
CHARGE
B5
B5
ISLA112P50
TO
TO
BIT 4
Reserved
Reserved
B12
B12
B4
B4
CLKP
CLKN
BIT 3
2 = +FS Short
3 = -FS Short
B11
B11
5 = reserved
6 = reserved
1 = Midscale
4 = Checker
B3
B3
Output Test Mode [3:0]
0 = Off
Board
Short
AVDD
AVDD
BIT 2
B10
B10
B2
B2
FIGURE 47. CLOCK INPUTS
11kO
11kO
Ω
Ω
9-15 = reserved
BIT 1
8 = User Input
7 = One/Zero
Word Toggle
B1
B9
B1
B9
AVDD
18kO
18kO
(LSB)
BIT 0
Ω
Ω
B0
B8
B0
B8
AVDD
VALUE
(Hex)
DEF.
00h
00h
00h
00h
00h
00h
GENERATION
June 17, 2010
INDEXED
/GLOBAL
CLOCK-
PHASE
TO
FN7604.1
G
G
G
G
G
G

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