NUTINY-SDK-M0516 Nuvoton Technology Corporation of America, NUTINY-SDK-M0516 Datasheet - Page 74

• Manufacturer Part Number: NUTINY-SDK-M0516
• Description: BOARD EVAL NUMICRO M051 SERIES
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r
• Type: MCUr

Specifications of NUTINY-SDK-M0516

• Contents: Board, Cable
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: M051™ Series, M052/M054/M058/M0516

6.2.8.3 Operation Description
6.2.8.4 NVIC Control Registers
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
R: read only, W: write only, R/W: both read and write
Register
SCS_BA = 0xE000_E000
NVIC_ISER
NVIC_ICER
NVIC_ISPR
NVIC_ICPR
NVIC_IPR0
NVIC_IPR1
NVIC_IPR2
NVIC_IPR3
NuMicro M051
Offset
SCS_BA+100
SCS_BA+180
SCS_BA+200
SCS_BA+280
SCS_BA+400
SCS_BA+404
SCS_BA+408
SCS_BA+40C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
™
Description
IRQ0 ~ IRQ31 Set-Enable Control Register
IRQ0 ~ IRQ31 Clear-Enable Control Register
IRQ0 ~ IRQ31 Set-Pending Control Register
IRQ0 ~ IRQ31 Clear-Pending Control Register
IRQ0 ~ IRQ3 Priority Control Register
IRQ4 ~ IRQ7 Priority Control Register
IRQ8 ~ IRQ11 Priority Control Register
IRQ12 ~ IRQ15 Priority Control Register
Series Technical Reference Manual
- 74 -
Publication Release Date: Sep 14, 2010
Revision V1.2
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000