C8051F380DK Silicon Laboratories Inc, C8051F380DK Datasheet - Page 25
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C8051F380DK
Manufacturer Part Number
C8051F380DK
Description
DEV KIT FOR C8051F380
Manufacturer
Silicon Laboratories Inc
Datasheet
1.TOOLSTICK381DC.pdf
(43 pages)
Specifications of C8051F380DK
Processor To Be Evaluated
C8051F380
Processor Series
C8051F38x
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-2012
25
SMBus Transfer Modes
The SMBus interface may be configured to operate as Master and/or
a Slave
At any particular time, it will be operating in one of the following four
modes:
Peripheral is in master mode any time a START is generated
SMBus interrupts are generated at the end of all SMBus byte frames:
Master transmitter (write operation)
Master receiver (read operation)
Slave transmitter (read operation)
Slave receiver (write operation)
Remains in Master mode until it loses an arbitration or generates a STOP
Receiver:
Transmitter:
•The interrupt for an ACK occurs before the ACK with hardware ACK generation
disabled
•The interrupt for an ACK occurs after the ACK when hardware ACK generation is
enabled
•Interrupts occur after the ACK