DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 19

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Table 3–26. Global Clock External I/O Timing Parameters for the 5M40Z, 5M80Z, 5M160Z, and 5M240Z Devices
Table 3–27. Global Clock External I/O Timing Parameters for the 5M240Z Device
January 2011 Altera Corporation
t
t
t
t
t
t
t
t
f
Notes to
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
(2) Not applicable to the T144 package of the 5M240Z device.
t
t
t
t
t
t
(Note
PD1
PD2
SU
H
CO
CH
CL
CNT
CNT
PD1
PD2
SU
H
CO
CH
Symbol
Symbol
clock input pin maximum frequency.
1),
Table
External Timing Parameters
(2)
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
Global clock hold time
Global clock to output delay
Global clock high time
Global clock low time
Minimum global clock period for
16-bit counter
Maximum global clock frequency for 16-bit
counter
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
Global clock hold time
Global clock to output delay
Global clock high time
3–26:
f
External timing parameters are specified by device density and speed grade. All
external I/O timing parameters shown are for the 3.3-V LVTTL I/O standard with the
maximum drive strength and fast slew rate. For external I/O timing using standards
other than LVTTL or for different drive strengths, use the I/O standard input and
output delay adders in
For more information about each external timing parameters symbol, refer to
AN629: Understanding Timing in Altera
Table 3–26
and 5M240Z devices.
Table 3–27
5M240Z device.
Parameter
Parameter
lists the external I/O timing parameters for the 5M40Z, 5M80Z, 5M160Z,
lists the external I/O timing parameters for the T144 package of the
Table 3–32 on page 3–22
Condition
Condition
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
—
—
—
—
—
—
—
—
—
CPLDs.
Min
253
253
Min
253
2.4
2.0
5.4
2.2
2.0
—
—
—
—
—
0
0
through
C4
C4
(Note
184.1
Max
Max
7.9
5.8
6.6
9.5
5.7
6.7
—
—
—
—
—
—
—
—
Table 3–36 on page
1),
(2)
Min
339
339
Min
339
4.6
2.0
8.4
4.4
2.0
—
—
—
—
—
0
0
C5, I5
C5, I5
MAX V Device Handbook
118.3
14.0
17.7
Max
Max
8.5
8.6
8.5
8.7
—
—
—
—
—
—
—
—
3–25.
MHz
Unit
Unit
ns
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ps
3–19