DC1298A-AA Linear Technology, DC1298A-AA Datasheet - Page 25

• Manufacturer Part Number: DC1298A-AA
• Description: BOARD EVAL LTM9002-AA
• Manufacturer: Linear Technology
• Type: Baseband Receiverr

Specifications of DC1298A-AA

• Design Resources: Demo Circuit 1298A Schematic
• Frequency: 0Hz ~ 300MHz
• Features: LTM9002 14bit Dual Receiver Subsystem, DC-170MHz LPF
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Mcu Supported Families: LTM9002
• Development Tool Type: Hardware - Eval/Demo Board
• For Use With/related Products: LTM9002
• Lead Free Status / RoHS Status: Not applicable / Not applicable

APPLICATIONS INFORMATION
Data Format
Using the MODE pin, the ADC parallel digital output can
be selected for offset binary or 2’s complement format.
Note that MODE controls both channel A and channel B.
Connecting MODE to GND or 1/3 V
binary output format. Connecting MODE to 2/3 V
V
resistive divider can be used to set the 1/3 V
V
MODE pin.
Table 7. MODE Pin Function
Overfl ow Bit
For LTM9002-AA, when OF outputs a logic high the con-
verter is either overranged or underranged on channel A
or channel B. Note that both channels share a common
OF pin. OF is disabled when channel A is in sleep or nap
mode. For LTM9002-LA, OFA and OFB indicate either
condition for the respective channel.
Output Clock
The LTM9002-AA has a delayed version of the CLKB input
available as a digital output, CLKOUT. The falling edge of
the CLKOUT pin can be used to latch the digital output
data. CLKOUT is disabled when channel B is in sleep or
nap mode.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
to the same supply that powers the logic being driven.
For example, if the converter drives a DSP powered by a
1.8V supply, then OV
supply.
DD
DD
selects 2’s complement output format. An external
logic values. Table 7 shows the logic states for the
MODE PIN
1/3V
2/3V
V
0
DD
DD
DD
DD
OUTPUT FORMAT
2’s Complement
2’s Complement
Straight Binary
Straight Binary
should be tied to that same 1.8V
DD
DD
CLOCK DUTY CYCLE
selects straight
, should be tied
STABILIZER
Off
On
On
Off
DD
or 2/3
DD
or
OV
3.6V, independent of V
voltage from GND up to 1V and must be less than OV
The logic outputs will swing between OGND and OV
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF . The
data access and bus relinquish times are too slow to allow
the outputs to be enabled and disabled during full-speed
operation. The output Hi-Z state is intended for use during
test or initialization. Channels A and B have independent
output enable pins (OEA, OEB.)
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting ADCSHDN to GND results
in normal operation. Connecting ADCSHDN to V
OE to V
circuitry including the reference and the ADC typically
dissipates 1mW. When exiting sleep mode, it will take
700μs to 1ms for the output data to become valid because
the reference capacitors have to recharge and stabilize.
Connecting ADCSHDN to V
nap mode and the ADC typically dissipates 30mW. In nap
mode, the on-chip reference circuit is kept on, so that
recovery from nap mode is faster than that from sleep
mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Channels A and B have independent ADCSHDN pins
(ADCSHDNA, ADCSHDNB.) Channel A is controlled by
ADCSHDNA and OEA, and channel B is controlled by
ADCSHDNB and OEB. The nap, sleep and output enable
modes of the two channels are completely independent,
so it is possible to have one channel operating while the
other channel is in nap or sleep mode.
Digital Output Multiplexer
The digital outputs of the ADC can be multiplexed onto a
single data bus. The MUX pin is a digital input that swaps
the two data busses. If MUX is high, channel A comes
out on DAx; channel B comes out on DBx. If MUX is low,
DD
can be powered with any voltage from 500mV up to
DD
results in sleep mode, which powers down all
DD
. OGND can be powered with any
DD
and OE to GND results in
LTM9002
25
DD
DD
and
9002f
DD
.
.