CS8415A-CS Cirrus Logic Inc, CS8415A-CS Datasheet
CS8415A-CS
Specifications of CS8415A-CS
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CS8415A-CS Summary of contents
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... Target applications include A/V receivers, CD-R, DVD receivers, multimedia speakers, digital mixing consoles, effects processors, set-top boxes, and computer and automotive audio systems. ORDERING INFOMATION CS8415A-CS 28-pin SOIC CS8415A-CZ 28-pin TSSOP -10 to +70°C CS8415A-IS CS8415A-IZ CDB8415A VL+ DGND ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 CS8415A DS470PP3 ...
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... Q-Channel Subcode Bytes (14h - 1Dh) (Read Only) ........................................... 29 8.17 OMCK/RMCK Ratio (1Eh) (Read Only).......................................................................... 29 8.18 C-bit or U-bit Data Buffer (1Fh - 37h) ............................................................................. 29 8.19 CS8415A I.D. and Version Register (7Fh) (Read Only) ................................................. 29 9. PIN DESCRIPTION - SOFTWARE MODE ............................................................................. 30 10. HARDWARE MODE ............................................................................................................. 32 10.1 Serial Audio Port Formats ............................................................................................. 32 11 ...
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... Reset high, VA+ Reset high, VL Reset high, VL (Note 1) ‘-IS’ & ‘-IZ’ (Note 2) (AGND, DGND = 0 V, all voltages with respect to ground) Symbol VL+,VA+ (Note CS8415A (AGND, DGND = 0 V, all voltages with respect Min Typ Max 4.5 5.0 5.5 2.85/4.5 3.0/5.0 3.15/5.5 - 6.3 ...
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... VA+ = 5V±10%, VL+ = 3/5V ±5/10 Symbol V IH (Note =0.4V (Max -40 to 85°C for ‘IS’ & ‘IZ’ ; VA+ = 5V±10%, VL+ = 3/5V ±5/10% , Inputs: A Symbol CS8415A Min Typ Max 2.0 - (VL+) + 0.3 -0.3 - 0.4/ 0 0.4 (VL ±1 ±10 - 200 ...
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... VA+ = 5V±10%, VL+ = 3/5V ±5/10% , Inputs pF) Symbol (Note 5) (Note 5) (Note 6) (Note 7) (Note 5,6,8) OLRCK (input) OSCLK (input) t lmd SDOUT Figure 2. Audio Port Slave Mode and Data Input Timing CS8415A Min Typ Max dpd smd ...
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... CCLK CDIN CDOUT DS470PP3 = -40 to 85°C for ‘IS’ & ‘IZ’ ; VA+ = 5V±10%, VL+ = 3/5V ±5/10% , Inputs pF) Symbol (Note 10) (Note 11) (Note 12) (Note 12) t scl t sch t css dsu Figure 3. SPI Mode Timing CS8415A Min Typ Max 6.0 sck t 1 csh css t 66 ...
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... C protocol and is supported only at 5V mode. Repeated Start t high t t sud t sust hdd Figure 4. Two-Wire Mode timing CS8415A Min Typ Max Units - - 100 kHz µs 4 µs 4 µs 4 µs 4 µs 4 µ ...
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... F VA+ VL+ CS8415A RXP6 RXP5 OLRCK RXP4 OSCLK RXP3 SDOUT RXP2 RXP1 RXP0 RXN0 SDA/CDOUT AD0/CS RMCK SCL/CCLK AD1/CDIN INT U EMPH / DGND2 RERR H/S RST AGND FILT DGND RFILT CFILT CRIP CS8415A +3V to +5V Digital Supply 3-wire Serial Audio Input Device Microcontroller 9 ...
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... GENERAL DESCRIPTION The CS8415A is a monolithic CMOS device which receives and decodes audio data according to the AES3, IEC60958, S/PDIF, and EIAJ CP1201 inter- face standards. Input data is either differential or single-ended. A low jitter clock is recovered from the incoming data using a PLL. The decoded audio data is output through a configurable, 3-wire output port ...
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... By appropriate phasing of the left/right clock and control of the se- rial clocks, multiple CS8415A’s can share one se- rial port. The left/right clock should be continuous, but the duty cycle can be less than the specified typ- ical value of 50% if enough serial clocks are present in each phase to clock all the data bits ...
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... See Serial Output Data Format Register Bit Descriptions for an explanation of the meaning of each bit 12 Left MSB LSB MSB Left LSB MSB Left MSB LSB Left MSB LSB SOSF* SORES[1:0]* SOJUST Figure 6. Serial Audio Output Example Formats CS8415A Right LSB MSB Right LSB MSB Right MSB LSB Right MSB SODEL* SOSPOL* SOLRPOL ...
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... The nominal center sample rate is the sample rate that the PLL first locks onto upon application of an AES3 data stream or after enabling the CS8415A clocks by setting the RUN control bit. If the 12.5% sample rate limit is exceeded, the PLL will return to its wide lock range mode and re-acquire a new nomi- nal center sample rate ...
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... Error Reporting and Hold Function While decoding the incoming AES3 data stream, the CS8415A can identify several kinds of error, indicated in the Receiver Error register. The UN- LOCK bit indicates whether the PLL is locked to the incoming AES3 data. The V bit reflects the cur- Fs Range (kHz) RFILT (kΩ ...
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... AC-3 or MPEG encoders, may not adhere to this convention, and the bit may not be properly set. The CS8415A AES3 receiver can detect such non-audio data. This is accomplished by looking for a 96-bit sync code, consisting of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872, and 0x4E1F ...
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... SDOUT. Using mono mode is only necessary if the serial au- dio output port must run at 96 kHz. If the CS8415A is kept in normal stereo mode, and receives AES3 data arranged in mono mode, then the serial audio output port will run at 48 kHz, with left and right data fields representing consecutive audio samples ...
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... AD0 bit address state. 6.1 SPI Mode In SPI mode the CS8415A chip select signal, CCLK is the control port bit clock (input into the CS8415A from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcontroller. Data is ...
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... Each byte is separated by an acknowledge bit. The ACK bit is output from the CS8415A after each input byte is read, and is input to the CS8415A from the microcontroller after each transmitted byte.The Two-Wire mode is compatible with the I2C Proto- col ...
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... AD 1 and AD 0 are determined by the state of the corresponding pins operation is a write, this byte contains the Memory Address Pointer, MAP operation is a read, the last bit of the read should be NACK (high). DS470PP3 Note 1 Note 2 AD2-0 ACK DATA7-0 ACK DATA7-0 ACK R/W EMPH CS8415A Note 3 Stop pin. 19 ...
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... INCR - Auto Increment Address Control Bit Default = ‘0’ Disabled 1 - Enabled MAP6:MAP0 - Register address Note: Reserved registers must not be written to during normal operation. Some reserved registers are used for test modes, which can completely alter the normal operation of the CS8415A SWCLK 0 ...
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... Default = ‘0’ Normal stereo operation and B subframes treated as consecutive samples of one channel of data. Data is duplicated to both left and right parallel outputs of the AES receiver block. The sample rate (Fs) is doubled compared to MMR=0 DS470PP3 HOLD0 RMCKF MMR CS8415A INT1 INT0 MUX2 MUX1 MUX0 21 ...
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... Reading and writing the U and C data buffers is not possible. Power consumption is low Normal part operation. This bit must be written to the 1 state to allow the CS8415A to begin operation. All input clocks should be stable in frequency and phase when RUN is set to 1. ...
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... DETC - C-buffer transfer interrupt. The source for this bit is true during the buffer transfer in the C bit buffer management process. RERR - A receiver error has occurred. The Receiver Error register may be read to determine the nature of the error which caused the interrupt. DS470PP3 CS8415A DETC 0 RERR 23 ...
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... In Level active mode, the INT interrupt pin becomes active during the in- terrupt condition. Be aware that the active level(Actice High or Low) only depends on the INT[1:0] bits. These regis- ters default to 00 Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved DETU CS8415A QCH DETCM 0 RERRM DETC1 0 RERR1 DETC0 0 RERR0 DS470PP3 ...
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... Auxiliary data is 8 bits long 1001 - 1111 Reserved PRO - Channel status block format indicator 0 - Received channel status block is in consumer format 1 - Received channel status block is in professional format DS470PP3 DETUM DETU1 0 0 DETU0 AUX1 AUX0 PRO CS8415A QCHM QCH1 0 0 QCH0 AUDIO COPY ORIG 25 ...
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... AUDIO - Audio indicator 0 - Received data is linearly coded PCM audio 1 - Received data is not linearly coded PCM audio COPY - SCMS copyright indicator 0 - Copyright asserted 1 - Copyright not asserted 26 CS8415A DS470PP3 ...
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... BIP - Bi-phase error bit. Updated on sub-frame boundaries error 1 - Bi-phase error. This indicates an error in the received bi-phase coding. PAR - Parity bit. Updated on sub-frame boundaries error 1 - Parity error DS470PP3 CCRC UNLOCK V CS8415A CONF BIP PAR 27 ...
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... Byte Mode Channel B information is displayed at the EMPH pin and in the receiver channel status reg- ister. Channel B information is output during control port reads when CAM is set to 0 (One Byte Mode CCRCM UNLOCKM BSEL CBMR DETCI CS8415A CONFM BIPM PARM CAM CHS DS470PP3 ...
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... Either channel status data buffer E or user data buffer E is accessible through these register addresses. 8.19 CS8415A I.D. and Version Register (7Fh) (Read Only ID3 ID2 ID3 code for the CS8415A. Permanently set to 0100 VER3:0 - CS8415A revision level. Revision A is coded as 0001 DS470PP3 ...
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... AN159 provides additional resources for the PLL. 9 Reset (Input) - When RST is low, the CS8415A enters a low power mode and all internal states are RST reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase ...
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... Hardware/Software Mode Control (Input) - Determines the method of controlling the operation of the H/S CS8415A, and the method of accessing CS and U data. In software mode, device control and CS and U data access is primarily through the control port, using a microcontroller. Hardware mode provides an alternate mode of operation and access to the CS and U data through dedicated pins. This pin should be ...
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... HARDWARE MODE The CS8415A has a hardware mode which allows using the device without a microcontroller. Hard- ware mode is selected by connecting the H/S pin to VL+. Various pins change function in hardware mode, described in the hardware mode pin defini- tion section. Hardware mode data flow is shown in Figure 11. ...
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... AN159 provides additional information about the PLL. 9 Reset (Input) - When RST is low, the CS8415A enters a low power mode and all internal states are RST reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase ...
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... Hardware/Software Mode Control (Input) - Determines the method of controlling the operation of the H/S CS8415A, and the method of accessing CS and U data. In software mode, device control and CS and U data access is primarily through the control port, using a microcontroller. Hardware mode provides an alternate mode of operation and access to the CS and U data through dedicated pins. This pin should be permanently tied to VL+ or DGND ...
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... APPLICATIONS 12.1 Reset, Power Down and Start-up When RST is low, the CS8415A enters a low pow- er mode and all internal states are reset, including the control port and registers, and the outputs are muted. When RST is high, the control port be- comes operational and the desired settings should be loaded into the control registers ...
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... JEDEC #: MS-013 Controlling Dimension is Millimeters CS8415A MILLIMETERS MIN NOM MAX 2.35 2.50 0.10 0.20 0.33 0.42 0.23 0.28 17.70 17.90 18.10 7 ...
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... BSC 9.60 BSC 0.2519 0.256 6.30 0.1732 0.177 4.30 -- 0.024 0.029 0.50 4° 8° JEDEC #: MO-153 Controlling Dimension is Millimeters. CS8415A END VIEW L PLANE MILLIMETERS NOM MAX -- -- 1.20 0.10 0.15 0.90 1.00 0.245 0.30 9.70 BSC 9.80 BSC 6 ...
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... APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS 14.1 AES3 Receiver External Components The CS8415A AES3 receiver is designed to accept both the professional and consumer interfaces. The digital audio specifications for professional use call for a balanced receiver, using XLR connectors, with 110 Ω ±20% impedance. The XLR connector on the receiver should have female pins with a male shell ...
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... DS470PP3 CS8415A 0.01 µF RXP0 RXN0 Figure 15. S/PDIF MUX Input Circuit 0.01 µF Gate 0.01 µF Figure 16. TTL/CMOS Input Circuit CS8415A .01µF 75 Ω 75 Ω Coax .01µF 75 Ω 75 Ω Coax .01µF 75 Ω 75 Ω Coax .01µF CS8415A RXP0 RXN0 RXP6 RXP5 . . . RXP0 RXN0 39 ...
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... Reserving the first 5 bytes in the E buffer buffer transfers periodically overwrite the data stored in the E buffer. The CS8415A has the capability of reserving the first 5 bytes of the E buffer for user writes only. When this capability is in use, internal buffer transfers will NOT af- fect the first 5 bytes of the E buffer ...
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... In these situations, two byte mode should be used to access the E buffer. In this mode, a read will cause the CS8415A to out- put two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data ...
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