DP83848HSQ National Semiconductor, DP83848HSQ Datasheet - Page 54
DP83848HSQ
Manufacturer Part Number
DP83848HSQ
Description
IC, TRANSCEIVER, ENET PHYTER, 40LLP
Manufacturer
National Semiconductor
Datasheet
1.DP83848HSQ.pdf
(80 pages)
Specifications of DP83848HSQ
Data Rate
100Mbps
No. Of Ports
1
Ethernet Type
IEEE 802.3u
Supply Current
92mA
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +125°C
Digital Ic Case Style
LLP
No. Of
RoHS Compliant
Interface Type
MII Serial, RMII
Rohs Compliant
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
www.national.com
7.2.7 PHY Control Register (PHYCR)
Bit
15
14
13
12
11
10
9
8
7
6
BIST_STATUS
BP_STRETCH
FORCE_MDIX
BIST_START
RESERVED
PAUSE_RX
PAUSE_TX
MDIX_EN
Bit Name
BIST_FE
PSR_15
Table 27. PHY Control Register (PHYCR), address 0x19
Strap, RW
0, RW/SC
0, LL/RO
Default
0, RW
0, RW
0, RW
0, RW
0, RO
0, RO
0
Auto-MDIX Enable:
1 = Enable Auto-neg Auto-MDIX capability.
0 = Disable Auto-neg Auto-MDIX capability.
The Auto-MDIX algorithm requires that the Auto-Negotiation En-
able bit in the BMCR register to be set. If Auto-Negotiation is not
enabled, Auto-MDIX should be disabled as well.
Force MDIX:
1 = Force MDI pairs to cross.
0 = Normal operation.
Pause Receive Negotiated:
Indicates that pause receive should be enabled in the MAC. Based
on ANAR[11:10] and ANLPAR[11:10] settings.
This function shall be enabled according to IEEE 802.3 Annex 28B
Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated High-
est Common Denominator is a full duplex technology.
Pause Transmit Negotiated:
Indicates that pause transmit should be enabled in the MAC. Based
on ANAR[11:10] and ANLPAR[11:10] settings.
This function shall be enabled according to IEEE 802.3 Annex 28B
Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated High-
est Common Denominator is a full duplex technology.
BIST Force Error:
1 = Force BIST Error.
0 = Normal operation.
This bit forces a single error, and is self clearing.
BIST Sequence select:
1 = PSR15 selected.
0 = PSR9 selected.
BIST Test Status:
1 = BIST pass.
0 = BIST fail. Latched, cleared when BIST is stopped.
For a count number of BIST errors, see the BIST Error Count in the
CDCTRL1 register.
BIST Start:
1 = BIST start.
0 = BIST stop.
Bypass LED Stretching:
This will bypass the LED stretching and the LED will reflect the in-
ternal value.
1 = Bypass LED stretching.
0 = Normal operation.
RESERVED: Must be zero.
(Receive on TPTD pair, Transmit on TPRD pair)
54
Description