DS90CR483VJD National Semiconductor, DS90CR483VJD Datasheet - Page 11

IC, LVDS CHANNEL LINK SER/DES, TQFP-100

DS90CR483VJD

Manufacturer Part Number
DS90CR483VJD
Description
IC, LVDS CHANNEL LINK SER/DES, TQFP-100
Manufacturer
National Semiconductor
Datasheet

Specifications of DS90CR483VJD

Supply Current
280mA
Supply Voltage Range
3V To 3.6V
Driver Case Style
TQFP
No. Of Pins
100
Operating Temperature Range
-10°C To +70°C
Device Type
Clock
Termination Type
SMD
Filter Terminals
SMD
Rohs Compliant
No
Data Rate Max
5380Mbps
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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AC Timing Diagrams
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
TPPOS — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + LVDS Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
RSKMD ≥ TPPOSvariance (d) + TJCC (output jitter)(f) + ISI (m)
See Applications Informations section for more details.
j
j
j
j
j
j
j
Cable Skew — typically 10 ps to 40 ps per foot, media dependent
TJCC — Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
ISI is dependent on interconnect length; may be zero
See Applications Informations section for more details.
d = Tppos — Transmitter output pulse position (min and max)
f = TJCC — Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
m = extra margin - assigned to ISI in long cable applications
FIGURE 13. Receiver Skew Margin (RSKM) without DESKEW
FIGURE 14. Receiver Skew Margin (RSKMD)with DESKEW
(Continued)
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