CAT9534WI-GT2 CATALYST SEMICONDUCTOR, CAT9534WI-GT2 Datasheet - Page 9

• Manufacturer Part Number: CAT9534WI-GT2
• Description: IC, I/O EXPANDER, 8BIT, 400KHZ, SOIC-16
• Manufacturer: CATALYST SEMICONDUCTOR

Specifications of CAT9534WI-GT2

• Chip Configuration: 8 Bit
• Bus Frequency: 400kHz
• Ic Interface Type: I2C, SMBus
• No. Of I/o's: 8
• Supply Voltage Range: 2.3V To 5.5V
• Digital Ic Case Style: SOIC
• No. Of Pins: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ACKNOWLEDGE
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8
bits of data. The SDA line remains stable LOW during
the HIGH period of the acknowledge related clock
pulse (Figure 5).
The CAT9534 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each 8-bit byte.
When the CAT9534 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT9534 will continue to transmit
data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a
STOP condition. The master must then issue a STOP
condition to return the CAT9534 to the standby power
mode and place the device in a known state.
REGISTERS AND BUS TRANSACTIONS
The CAT9534 consists of an input port register, an
output port register, a polarity inversion register and a
configuration register. Table 1 shows the register
address table. Tables 2 to 5 list Register 0 through
Register 3 information.
Table 1. Register Command Byte
© 2010 SCILLC. All rights reserved
Characteristics subject to change without notice
Command
(hex)
0x00
0x01
0x02
0x03
FROM TRANSMITTER
FROM RECEIVER
DATA OUTPUT
DATA OUTPUT
SCL FROM
Read/write byte
Read/write byte
Read/write byte
MASTER
Read byte
Protocol
START
BUS RELEASE DELAY (TRANSMITTER)
Polarity inversion register
Configuration register
Output port register
Input port register
1
Function
Figure 7. Acknowledge Timing
ACK DELAY
9
The command byte is the first byte to follow the device
address byte during a write/read bus transaction. The
register command byte acts as a pointer to determine
which register will be written or read.
The input port register is a read only port. It reflects
the incoming logic levels of the I/O pins, regardless of
whether the pin is defined as an input or an output by
the configuration register. Writes to the input port
register are ignored.
Table 2. Register 0 – Input Port Register
Table 3. Register 1 – Output Port Register
Table 4. Register 2 – Polarity Inversion Register
Table 5. Register 3 – Configuration Register
8
default
default
default
default
bit
bit
bit
bit
O
N
C
I
1
1
0
1
7
7
7
7
9
ACK SETUP
O
N
C
I
1
1
0
1
6
6
6
6
O
N
C
BUS RELEASE DELAY (RECEIVER)
I
1
1
0
1
5
5
5
5
O
N
C
I
1
1
0
1
4
4
4
4
O
N
C
I
1
0
1
1
3
3
3
3
O
C
N
1
I
1
1
0
Doc. No. MD-9004 Rev. D
2
2
2
2
O
N
C
I
1
1
0
1
1
CAT9534
1
1
1
O
N
C
I
1
1
0
1
0
0
0
0