DSPIC30F4011-20E/P Microchip Technology, DSPIC30F4011-20E/P Datasheet - Page 12

• Manufacturer Part Number: DSPIC30F4011-20E/P
• Description: IC, DSC, 16BIT, 48KB, 40MHZ, 5.5V, DIP40
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F4011-20E/P

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F003 - MODULE SOCKET DSPIC30F 40DIPACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: DSPIC30F4011-20EP

dsPIC30F Family Reference Manual
35.3.2.2
35.3.2.2.1 Slave Select Synchronization
DS70272B-page 35-12
Slave Mode
In Slave mode, data is transmitted and received as the external clock pulses appear on the SCK1
pin. The CKP (SPI1CON<6>) and CKE (SPI1CON<8>) bits determine on which edge of the clock
data transmission occurs. Both data to be transmitted and data that is received are, respectively,
written into or read from the SPI1BUF register. The rest of the operation of the module is identical
to that described above for the Master mode.
To set up the SPI1 module for the Slave mode of operation, perform the following steps:
1.
2.
3.
4.
5.
6.
7.
Example 35-2 shows a code snippet for configuring the SPI register for the Slave mode.
Example 35-2:
The SS1 pin allows the Synchronous Slave mode. If the SSEN (SPI1CON1<7>) bit is set,
transmission and reception are enabled in Slave mode only if the SS1 pin is driven to a low state
(see Figure 35-5). To ensure that the SS1 pin can function correctly as an input, the port output
or other peripheral outputs multiplexed with the SS1 pin function must not be used. If the SSEN
bit is set and the SS1 pin is driven high, the SDO1 pin is no longer driven and will tri-state even
if the module is in the middle of a transmission.
An aborted transmission will be retried, using the data held in the SPI1TXB register, the next time
the SS1 pin is driven low. If the SSEN bit is not set, the SS1 pin does not affect the module
operation in Slave mode.
/* Following code snippet shows SPI register configuration for SLAVE mode*/
IFS0bits.SPI1IF = 0;
IEC0bits.SPI1IE = 0;
SPI1CON1bits.DISSCK = 0;
SPI1CON1bits.DISSDO = 0;
SPI1CON1bits.MODE16 = 1;
SPI1CON1bits.SMP = 0;
SPI1CON1bits.CKE = 0;
SPI1CON1bits.CKP = 0;
SPI1CON1bits.MSTEN = 0;
SPI1STATbits.SPIROV=0;
SPI1STATbits.SPIEN = 1;
IFS0bits.SPI1IF = 0;
IEC0bits.SPI1IE = 1;
Note:
Clear the SPI1BUF register.
If using interrupts:
a)
b)
c)
Write the desired settings to the SPI1CON1 and SPI1CON2 registers with MSTEN
(SPI1CON1<5>) = 0.
Clear the SMP bit.
If the CKE bit is set, then the SSEN bit (SPI1CON1<7>) must be set to enable the SS1 pin.
Clear the SPIROV bit (SPI1STAT<6>).
Enable SPI1 operation by setting the SPIEN bit (SPI1STAT<15>).
Clear the SPI1IF bit in the IFS0 register.
Set the SPI1IE bit in the IEC0 register.
Write the SPI1IP bits in the IPC2 register to set the interrupt priority.
To meet module timing requirements, the SS1 pin must be enabled in Slave mode
when CKE = 1 (refer to Figure 35-6 for details).
SPI Configuration – Slave Mode
//Clear the Interrupt Flag
//Disable The Interrupt
// SPI1CON1 Register Settings
//Internal Serial Clock is Enabled.
//SDO1 pin is controlled by the module.
//Communication is word-wide (16 bits).
//Input Data is sampled at the middle of data
//output time.
//Serial output data changes on transition
//from Idle clock state to active clock state
//Idle state for clock is a low level; active
//state is a high level
//Master Mode disabled
//No Receive Overflow Has Occurred
//Enable SPI Module
//Interrupt Controller Settings
//Clear the Interrupt Flag
//Enable The Interrupt
© 2008 Microchip Technology Inc.