DSPIC30F4011-20E/P Microchip Technology, DSPIC30F4011-20E/P Datasheet - Page 15

• Manufacturer Part Number: DSPIC30F4011-20E/P
• Description: IC, DSC, 16BIT, 48KB, 40MHZ, 5.5V, DIP40
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F4011-20E/P

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F003 - MODULE SOCKET DSPIC30F 40DIPACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: DSPIC30F4011-20EP

Figure 35-6:
35.3.3
© 2008 Microchip Technology Inc.
SS1
SCK Input
(CKP = 0
CKE = 1)
SCK Input
(CKP = 1
CKE = 1)
SDO
Output
SDI Input
(SMP = 0)
Input
Sample
(SMP = 0)
SPI1IF
SPITBF
SPIRBF
Note 1: Operation for 8-bit mode is shown; the 16-bit mode is similar.
(2,3)
Write to
SPI1BUF
2: The SS1 pin must be used for Slave mode operation when CKE = 1.
3: When the SSEN (SPI1CON1<7>) bit is set to ‘1’, the SS1 pin must be driven low to enable transmission and
4: Transmit data is held in SPI1TXB and SPITBF remains set until all bits are transmitted.
(4)
Framed SPI Modes
reception in Slave mode.
SPI1 Slave Mode Timing (CKE = 1)
Section 35. Serial Peripheral Interface (SPI) (Part II)
The SPI1 module supports a basic framed SPI protocol while operating in either Master or Slave
modes. The module uses four control bits to configure framed SPI operation:
• FRMEN (SPI1CON2<15>) enables the Framed SPI modes and causes the SS1 pin to be
• SPIFSD (SPI1CON2<14>) determines whether the SS1 pin is an input or an output (i.e.,
• FRMPOL (SPI1CON2<13>) selects the polarity of the frame synchronization pulse
• FRMDLY (SPI1CON2<1>) selects whether the synchronization pulse coincides with or
used as a frame synchronization pulse input or output pin. The state of SSEN
(SPI1CON1<7>) is ignored.
whether the module receives or generates the frame synchronization pulse).
(active-high or active-low) for a single SPI data frame.
precedes the first serial clock pulse.
bit 7
bit 7
bit 6
bit 5
(1)
bit 4
bit 3
bit 2
SPI1SR to
SPI1RXB
bit 1
bit 0
bit 0
DS70272B-page 35-15
35