LFE2-20E-5QN208C LATTICE SEMICONDUCTOR, LFE2-20E-5QN208C Datasheet - Page 125

• Manufacturer Part Number: LFE2-20E-5QN208C
• Description: IC, LATTICEECP2 FPGA, 420MHZ, QFP-208
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2r

Specifications of LFE2-20E-5QN208C

• No. Of Logic Blocks: 21000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 5
• No. Of I/o's: 131
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 276Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.)
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one-to-one
connection with a package ball or pin.
Number
Pin
136
137
138
139
140
141
142
143
144
Function
Pin/Pad
VCCAUX
VCCIO0
PT6B
PT6A
PT4B
PT4A
PT2B
PT2A
GND
Bank
LFE2-6E/SE
0
0
0
0
0
0
0
-
-
Dual Function
VREF2_0
VREF1_0
Differential
4-25
C
C
C
T
T
T
Function
Pin/Pad
VCCAUX
VCCIO0
PT16B
PT16A
PT6B
PT6A
PT2B
PT2A
GND
LatticeECP2/M Family Data Sheet
Bank
0
0
0
0
0
0
0
-
-
LFE2-12E/12SE
Function
VREF2_0
VREF1_0
Dual
Pinout Information
Differential
C
C
C
T
T
T