LFE2M50E-6FN484C LATTICE SEMICONDUCTOR, LFE2M50E-6FN484C Datasheet - Page 32

• Manufacturer Part Number: LFE2M50E-6FN484C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-484
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M50E-6FN484C

• No. Of Logic Blocks: 48000
• No. Of Macrocells: 24000
• No. Of Speed Grades: 6
• No. Of I/o's: 270
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 4147Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-28. PIC Diagram
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-28.
The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right
edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs.
DDRCLKPOL*
*Signals are available on left/right/bottom edges only.
** Selected blocks.
DQSXFER*
QNEG0*
QNEG1*
ONEG2*
QPOS0*
QPOS1*
OPOS2*
ONEG0
OPOS0
ONEG1
INDD
OPOS1
INCK**
ECLK1
ECLK2
IPOS0
IPOS1
GSRN
INFF
CLK
LSR
CE
TD
Control
Muxes
CLK1
CLK0
CEO
GSR
LSR
CEI
2-29
PIOA
Register
Register
Register
Tristate
Output
Block
Block
Block
Input
PIOB
IOLD0
IOLT0
DI
LatticeECP2/M Family Data Sheet
Buffer
sysIO
PADB
PADA
“C”
“T”
Architecture