EPM7256AEFC256-10N Altera, EPM7256AEFC256-10N Datasheet - Page 7
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EPM7256AEFC256-10N
Manufacturer Part Number
EPM7256AEFC256-10N
Description
IC PLD EEPROM 256 MACROCELL FBGA-256
Manufacturer
Altera
Series
MAX 7000AEr
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7256AEFC256-10N
Cpld Type
EEPROM
No. Of Macrocells
256
No. Of I/o's
164
Propagation Delay
10ns
Global Clock Setup Time
3.9ns
Frequency
172.4MHz
Supply Voltage Range
3V To 3.6V
Family Name
MAX 7000A
Memory Type
EEPROM
# Macrocells
256
Number Of Usable Gates
5000
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
16
# I/os (max)
164
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7256AEFC256-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
Figure 1. MAX 7000A Device Block Diagram
Note:
(1)
EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enables.
EPM7512AE devices have 10 output enables.
INPUT/OE2/GCLK2
INPUT/GCLRn
INPUT/GCLK1
INPUT/OE1
2 to 16 I/O
2 to 16 I/O
6 or 10 Output Enables (1)
Control
Control
Block
Block
I/O
I/O
Logic Array Blocks
The MAX 7000A device architecture is based on the linking of
high-performance LABs. LABs consist of 16-macrocell arrays, as shown in
Figure
is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
6
6
2 to 16
2 to 16
2 to 16
2 to 16
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Direct input paths from I/O pins to the registers that are used for fast
setup times
1. Multiple LABs are linked together via the PIA, a global bus that
LAB A
LAB C
Macrocells
Macrocells
33 to 48
1 to 16
2 to 16
2 to 16
16
16
36
36
MAX 7000A Programmable Logic Device Data Sheet
PIA
36
36
2 to 16
2 to 16
16
16
Macrocells
Macrocells
17 to 32
49 to 64
LAB D
LAB B
6 or 10 Output Enables (1)
2 to 16
2 to 16
2 to 16
2 to 16
Control
Control
Block
Block
I/O
I/O
6
6
2 to 16 I/O
2 to 16 I/O
7