ISPLSI2064A-100LJN84 LATTICE SEMICONDUCTOR, ISPLSI2064A-100LJN84 Datasheet - Page 10

• Manufacturer Part Number: ISPLSI2064A-100LJN84
• Description: IC, PLD, EEPROM 64 MACROCELL 10NS LCC-84
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: IspLSI 2064Ar

Specifications of ISPLSI2064A-100LJN84

• Cpld Type: EEPROM
• No. Of Macrocells: 64
• No. Of I/o's: 64
• Propagation Delay: 10ns
• Global Clock Setup Time: 6.5ns
• Frequency: 100MHz
• Supply Voltage Range: 4.75V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
Pin Description
GND
VCC
GOE 0, GOE 1
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
Y0, Y1, Y2
RESET
ispEN
SDI/IN 0
MODE/IN 1
SDO/IN 2
SCLK/IN 3
NC
1
NAME
2
2
2
2
TQFP PIN NUMBERS
13,
12,
17,
21,
29,
33,
40,
44,
48,
56,
67,
71,
79,
83,
90,
94,
98,
11,
15
14
16
37
39
60
1,
25,
50,
74,
89,
66,
6,
38,
64
18,
22,
30,
34,
41,
45,
53,
57,
68,
72,
80,
84,
91,
95,
65,
2,
26,
51,
75,
99,
87
3,
7,
63,
19,
23,
31,
35,
42,
46,
54,
58,
69,
73,
81,
85,
92,
96,
62
10,
27,
52,
76,
100
4,
8,
88
20,
28,
32,
36,
43,
47,
55,
59,
70,
78,
82,
86,
93,
97,
24,
49,
61,
77,
5,
9
Global Output Enable input pins.
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
Ground (GND)
V
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Active Low (0) Reset pin which resets all of the registers in the device.
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK controls become active.
Input – This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN 0 also is used as one of the two control pins for the ISP state
machine. When ispEN is high, it functions as a dedicated input pin.
Input – This pin performs two functions. When ispEN is logic low, it
functions as a pin to control the operation of the ISP state machine.
When ispEN is high, it functions as a dedicated input pin.
Output/Input – This pin performs two functions. When ispEN is logic
low, it functions as an output pin to read serial shift register data. When
ispEN is high, it functions as a dedicated input pin.
Input – This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. When ispEN is
high, it functions as a dedicated input pin.
No Connect.
CC
10
Specifications ispLSI 2064/A
DESCRIPTION
Table 2-0002-2064b.eps