ISPLSI2064A-100LJN84 LATTICE SEMICONDUCTOR, ISPLSI2064A-100LJN84 Datasheet - Page 9

• Manufacturer Part Number: ISPLSI2064A-100LJN84
• Description: IC, PLD, EEPROM 64 MACROCELL 10NS LCC-84
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: IspLSI 2064Ar

Specifications of ISPLSI2064A-100LJN84

• Cpld Type: EEPROM
• No. Of Macrocells: 64
• No. Of I/o's: 64
• Propagation Delay: 10ns
• Global Clock Setup Time: 6.5ns
• Frequency: 100MHz
• Supply Voltage Range: 4.75V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
Pin Description
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
GOE 0, GOE 1
Y0, Y1, Y2
RESET
ispEN
SDI/ IN 0
MODE/ IN 1
SDO/IN 2
SCLK/IN 3
GND
VCC
NC
1
NAME
2
2
2
2
PLCC PIN NUMBERS
20,
26,
30,
34,
38,
45,
49,
53,
57,
68,
72,
76,
80,
3,
7,
11,
15,
67,
24
23
25
42
44
61
1,
21,
2,
27,
31,
35,
39,
46,
50,
54,
58,
69,
73,
77,
81,
4,
8,
12,
16,
84
66,
22,
65
19,
28,
32,
36,
40,
47,
51,
55,
59,
70,
74,
78,
82,
5,
9,
13,
17,
63
43,
62
29,
33,
37,
41,
48,
52,
56,
60,
71,
75,
79,
83,
6,
10,
14,
18
64
Input — This pin performs two functions. When ispEN is logic low, it functions
as a pin to control the operation of the ISP state machine. When ispEN is high,
it functions as a dedicated input pin.
Input/Output Pins — These are the general purpose I/O pins used by the logic
array.
Global Output Enable input pins.
Dedicated Clock input. This clock input is connected to one of the clock inputs of
all the GLBs in the device.
Input — This pin performs two functions. When ispEN is logic low, it functions
as an input pin to load programming data into the device. SDI/IN 0 also is used
as one of the two control pins for the ISP state machine. When ispEN is high, it
functions as a dedicated pin input.
Input — This pin performs two functions. When ispEN is logic low, it functions
as a clock pin for the Serial Shift Register. When ispEN is high, it functions as
a dedicated input pin.
Ground (GND)
Vcc
Active Low (0) Reset pin which resets all registers in the device.
Input — Dedicated in-system programming enable pin. This pin is brought low to
enable the programming mode. When low, the MODE, SDI, SDO and SCLK
controls become active.
Output/Input — This pin performs two functions. When ispEN is logic low, it
functions as an output pin to read serial shift register data. When ispEN is high,
it functions as a dedicated input pin.
No Connect
9
Specifications ispLSI 2064/A
DESCRIPTION
Table 2-0002A-08isp/2064