S29AL016J70TFI020 Spansion Inc., S29AL016J70TFI020 Datasheet - Page 39

• Manufacturer Part Number: S29AL016J70TFI020
• Description: IC, FLASH, 16MBIT, 70NS, TSOP-48
• Manufacturer: Spansion Inc.

Specifications of S29AL016J70TFI020

• Memory Type: Flash
• Memory Size: 16Mbit
• Memory Configuration: 2M X 8 / 1M X 16
• Ic Interface Type: CFI, Parallel
• Access Time: 70ns
• Supply Voltage Range: 2.7 To 3.6 V
• Memory Case Style: TSOP
• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.5
February 18, 2010 S29AL016J_00_10
Reading Toggle Bits DQ6/DQ2
Refer to
toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling,
the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on
the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or
erase operation. If it is still toggling, the device did not complete the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of
Notes
1. Read toggle bit twice to determine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.
Figure 11.2 on page 39
D a t a
(Notes 1, 2)
for the following discussion. Whenever the system initially begins reading
S h e e t
No
Figure 11.2 Toggle Bit Algorithm
S29AL016J
Figure 11.2 on page
Complete, Write
Reset Command
Read DQ7–DQ0
Read DQ7–DQ0
Read DQ7–DQ0
Program/Erase
Operation Not
Toggle Bit
DQ5 = 1?
Toggle Bit
= Toggle?
= Toggle?
START
Twice
Yes
Yes
Yes
(Note 1)
Operation Complete
No
No
Program/Erase
39).
39