SST39VF1682-70-4C-EKE SILICON STORAGE TECHNOLOGY, SST39VF1682-70-4C-EKE Datasheet - Page 3

• Manufacturer Part Number: SST39VF1682-70-4C-EKE
• Description: IC, FLASH, 16MB, 70NS, TSOP-48
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST39VF1682-70-4C-EKE

• Memory Type: Flash
• Memory Size: 16MB
• Ic Interface Type: Parallel
• Access Time: 70ns
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Chip-Erase Operation
The SST39VF168x provide a Chip-Erase operation, which
allows the user to erase the entire memory array to the “1”
state. This is useful when the entire device must be quickly
erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address AAAH in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 6 for the command sequence, Figure 9 for tim-
ing diagram, and Figure 23 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored. When WP# is low, any attempt to Chip-Erase will
be ignored. During the command sequence, WP# should
be statically held high or low.
Write Operation Status Detection
The SST39VF168x provide two software means to detect
the completion of a Write (Program or Erase) cycle, in
order to optimize the system write cycle time. The software
detection includes two status bits: Data# Polling (DQ
Toggle Bit (DQ
enabled after the rising edge of WE#, which initiates the
internal Program or Erase operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data# Poll-
ing or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
Data# Polling (DQ
When the SST39VF168x are in the internal Program oper-
ation, any attempt to read DQ
ment of the true data. Once the Program operation is
completed, DQ
though DQ
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase oper-
ation, any attempt to read DQ
internal Erase operation is completed, DQ
©2003 Silicon Storage Technology, Inc.
7
may have valid data immediately following the
7
6
). The End-of-Write detection mode is
will produce true data. Note that even
7
)
7
7
will produce a ‘0’. Once the
7
will produce the comple-
or DQ
6
. In order to pre-
7
will produce a
7
) and
3
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 6 for
Data# Polling timing diagram and Figure 20 for a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
stop toggling. The device is then ready for the next opera-
tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ
is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ
Erase-Suspended Sector/Block. If Program operation is ini-
tiated in a sector/block not selected in Erase-Suspend
mode, DQ
An additional Toggle Bit is available on DQ
used in conjunction with DQ
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ
pulse of Write operation. See Figure 7 for Toggle Bit timing
diagram and Figure 20 for a flowchart.
TABLE 1: W
Note: DQ
Status
Normal
Operation
Erase-
Suspend
Mode
6
2
will be set to “1” if a Read operation is attempted on an
) is valid after the rising edge of the last WE# (or CE#)
status information.
7
and DQ
6
Standard
Program
Standard
Erase
Read from
Erase Suspended
Sector/Block
Read from
Non- Erase Suspended
Sector/Block
Program
will toggle.
RITE
2
require a valid address when reading
O
PERATION
6
6
to check whether a particular
Preliminary Specifications
will produce alternating “1”s
S
DQ
DQ
DQ
Data
TATUS
0
1
7
7
7
#
#
S71243-03-000
Toggle
Toggle
Toggle
DQ
Data
2
1
, which can be
6
No Toggle
Toggle
Toggle
6
DQ
Data
T1.0 1243
N/A
bit will
2
11/03
6
)