PIC18F452I/L Microchip Technology, PIC18F452I/L Datasheet - Page 115

• Manufacturer Part Number: PIC18F452I/L
• Description: IC, 8BIT MCU, PIC18F, 40MHZ, LCC-44
• Manufacturer: Microchip Technology

Specifications of PIC18F452I/L

• Controller Family/series: PIC18
• No. Of I/o's: 34
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Core Size: 8 Bit
• Program Memory Size: 16 KWords
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.0
The Timer3 module timer/counter has the following
features:
• 16-bit timer/counter
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• RESET from CCP module trigger
REGISTER 13-1:
© 2006 Microchip Technology Inc.
(two 8-bit registers; TMR3H and TMR3L)
TIMER3 MODULE
bit 7
bit 6-3
bit 5-4
bit 2
bit 1
bit 0
T3CON: TIMER3 CONTROL REGISTER
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register Read/Write of Timer3 in one 16-bit operation
0 = Enables register Read/Write of Timer3 in two 8-bit operations
T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x = Timer3 is the clock source for compare/capture CCP modules
01 = Timer3 is the clock source for compare/capture of CCP2,
00 = Timer1 is the clock source for compare/capture CCP modules
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T1CKI
0 = Internal clock (F
TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
Legend:
R = Readable bit
- n = Value at POR
R/W-0
RD16
(on the rising edge after the first falling edge)
Timer1 is the clock source for compare/capture of CCP1
T3CCP2
R/W-0
OSC
T3CKPS1
/4)
R/W-0
W = Writable bit
’1’ = Bit is set
T3CKPS0
R/W-0
Figure 13-1 is a simplified block diagram of the Timer3
module.
Register 13-1 shows the Timer3 control register. This
register controls the Operating mode of the Timer3
module and sets the CCP clock source.
Register 11-1 shows the Timer1 control register. This
register controls the Operating mode of the Timer1
module, as well as contains the Timer1 oscillator
enable bit (T1OSCEN), which can be a clock source for
Timer3.
T3CCP1
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
T3SYNC
R/W-0
PIC18FXX2
TMR3CS
x = Bit is unknown
R/W-0
DS39564C-page 113
TMR3ON
R/W-0
bit 0