PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 60
PIC24FJ64GB004-I/ML
Manufacturer Part Number
PIC24FJ64GB004-I/ML
Description
IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24FJ32GA102-ISP.pdf
(48 pages)
2.PIC24FJ32GB002-ISO.pdf
(352 pages)
3.PIC24FJ32GB002-ISO.pdf
(12 pages)
4.PIC24FJ32GB002-ISO.pdf
(342 pages)
Specifications of PIC24FJ64GB004-I/ML
Controller Family/series
PIC24
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
Interface
I2C, LIN, SPI, UART, USB
No. Of Pwm Channels
5
Core Size
16 Bit
Program Memory Size
64 KB
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Embedded Interface Type
I2C, LIN, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ64GB004-I/ML
Manufacturer:
MICROCHIP
Quantity:
1 200
- PIC24FJ32GA102-ISP PDF datasheet
- PIC24FJ32GB002-ISO PDF datasheet #2
- PIC24FJ32GB002-ISO PDF datasheet #3
- PIC24FJ32GB002-ISO PDF datasheet #4
- Current page: 60 of 352
- Download datasheet (3Mb)
PIC24FJ64GB004 FAMILY
EXAMPLE 5-4:
EXAMPLE 5-5:
EXAMPLE 5-6:
DS39940D-page 60
// C example using MPLAB C30
//Set up NVMCON for row programming
//Set up pointer to the first memory location to be written
//Perform TBLWT instructions to write necessary number of latches
for(i=0; i < 2*NUM_INSTRUCTION_PER_ROW; i++)
// C example using MPLAB C30
asm("DISI #5");
__builtin_write_NVM();
#define NUM_INSTRUCTION_PER_ROW 64
unsigned int offset;
unsigned int i;
unsigned long progAddr = 0xXXXXXX;
unsigned int progData[2*NUM_INSTRUCTION_PER_ROW];
NVMCON = 0x4001;
TBLPAG = progAddr>>16;
offset = progAddr & 0xFFFF;
{
}
__builtin_tblwtl(offset, progData[i++]);
__builtin_tblwth(offset, progData[i]);
offset = offset + 2;
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
BTSC
BRA
#5
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
NVMCON, #15
$-2
LOADING THE WRITE BUFFERS – ‘C’ LANGUAGE CODE
INITIATING A PROGRAMMING SEQUENCE – ASSEMBLY LANGUAGE CODE
INITIATING A PROGRAMMING SEQUENCE – ‘C’ LANGUAGE CODE
// Block all interrupts with priority < 7
// for next 5 instructions
// Perform unlock sequence and set WR
; Block all interrupts with priority <7
; for next 5 instructions
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
;
;
; and wait for it to be
; completed
// Buffer of data to write
// Write to address low word
// Write to upper byte
// Address of row to write
// Initialize NVMCON
// Initialize PM Page Boundary SFR
// Initialize lower word of address
// Increment address
2010 Microchip Technology Inc.
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