LM2743MTC National Semiconductor, LM2743MTC Datasheet - Page 15

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LM2743MTC

Manufacturer Part Number
LM2743MTC
Description
SYNC SW CONTROL, 3V:6V, POWERWISE
Manufacturer
National Semiconductor
Datasheet

Specifications of LM2743MTC

Primary Input Voltage
16V
No. Of Outputs
1
Output Voltage
13.5V
Output Current
20A
Voltage Regulator Case Style
TSSOP
No. Of Pins
14
Operating Temperature Range
-40°C To +125°C
Svhc
No SVHC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Application Information
In this example, in order to maintain a 2% peak-to-peak
output voltage ripple and a 40% peak-to-peak inductor cur-
rent ripple, the required maximum ESR is 15mΩ.The Sanyo
4SP560M aluminum electrolytic capacitor will give an
equivalent ESR of 14mΩ. The capacitance of 560µF is
enough to supply even severe load transients.
MOSFETs
MOSFETs are the critical parts of any switching controller.
Both, the control high side FET and the synchronous low
side FET, have a direct impact on the system efficiency.
In this case the target efficiency for typical application circuit
is about 89%. This variable will determine which MOSFET is
acceptable to use for the design.
Loss from the capacitors, inductors, and IC come to about
0.27W. This leaves about 0.33W for the FET switching,
conduction, and gate charging losses to meet the target
efficiency. All the losses are detailed in the Efficiency section.
The switching loss is particularly difficult to estimate because
it depends on many factors. When the load current is more
than about 1 or 2 amps, conduction losses outweigh the
switching and gate charging losses. This allows FET selec-
tion based on the R
switching and gate charging losses about 0.27W leaves for
conduction losses. When plugged MOSFET, the FDS6898A
with a typical R
ciency section for P
Control Loop Components
The Typical Application Circuit has been compensated to
improve the DC gain and bandwidth. The result of this com-
pensation is better line and load transient responses. For the
LM2743, the top feedback divider resistor, R
part of the compensation. For the 3.3V to 1.2V at 4A design,
the values are:
C
R
These values give a phase margin of 53˚ and a bandwidth of
80kHz.
EFFICIENCY CALCULATIONS
A reasonable estimation of the efficiency of a switching buck
controller can be obtained by adding together the Output
Power (P
The Output Power (P
design is (1.2V * 4A) = 4.8W. The Total Power (P
an efficiency calculation to complement the design, is shown
below.
The majority of the power losses are due to low and high
side of MOSFET’s losses. The losses in any MOSFET are
group of switching (P
FET Switching Loss (P
C1
C2
= 2.55kΩ, R
= 27pF, C
P
OUT
FET
P
SW
) loss and the Total Power (P
= P
C2
= 0.5 * V
DS(ON)
P
FB2
SW
SW
= 1200nF, C
CND
DS(ON)
= 10kΩ.
+ P
P
SW
= P
OUT
of 13mΩ, into the equation from Effi-
FET
) and conduction losses(P
CC
the loss come to be about 0.27W.
CND
SW
SW(ON)
) for theTypical Application Circuit
= 331.4mW
of the FET. After adding the FET
)
* I
= 61.38mW + 270mW
OUT
C3
+ P
= 3300pF, R
* (t
SW(OFF)
r
+ t
f
)* F
(Continued)
TOTAL
OSC
FB2
C1
) loss:
TOTAL
, is also a
= 40.2kΩ,
CND
), with
).
15
The FDS6898A has a typical turn-on rise time t
fall time t
losses for this type of dual N-Channel MOSFETs are
0.061W.
FET Conduction Loss (P
R
to account for the increasing R
ing.
There are few additional losses that are taken into account:
IC Operating Loss (P
where I
FET Gate Charging Loss (P
The value n is the total number of FETs used and Q
typical gate-source charge value, which is 3nC. For the
FDS6898A the gate charging loss is 5.94mW.
Input Capacitor Loss (P
Where,
n is the number of capacitors, and ESR is equivalent series
resistance.
Output Inductor Loss (P
where DCR
Total System Efficiency
DS(ON)
Q-VCC
= 13mΩ and the factor is a constant value (k = 1.3)
P
P
f
CND2
P
SW
P
of 15ns and 16ns, respectively. The switching
P
IOUT
CND
P
CND1
CND2
P
is the typical operating V
GATE
P
= 0.5 x 3.3V x 4A x 300kHz x 31ns
CND1
P
GATE
= (4A)
= 98.42mW + 172mW = 270mW
IC
is the direct current resistance
P
P
= (4A)
= I
= 1.5mA *3.3V = 4.95mW
IND
P
CND
= 2 x 3.3V x 3nC x 300kHz
P
= I
IND
P
IC
= n * V
P
2
P
2
OUT
P
IC)
GATE
= I
SW
2
CAP
= I
IND
x 13mΩ x 1.3 x (1 - 0.364)
OUT
= P
= (4A)
2
2
CAP
IND
CND
x 13mΩ x 1.3 x 0.364
OUT
= 61.38mW
Q_VCC
x R
CND1
= 88.8mW
= 176mW
= 5.94mW
x R
CC
)
)
GATE
)
DS(ON)
* DCR
2
DS(ON)
* Q
DS(ON)
x 11mΩ
+ P
x V
)
GS
CC
CND2
x k x (1-D)
IOUT
of a FET due to heat-
* F
CC
x k x D
,
OSC
,
current
r
and turn-off
www.national.com
GS
is the

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