AD7719BRUZ Analog Devices Inc, AD7719BRUZ Datasheet - Page 10

• Manufacturer Part Number: AD7719BRUZ
• Description: Dual 16-Bit & 24-Bit SD ADC
• Manufacturer: Analog Devices Inc

Specifications of AD7719BRUZ

• Number Of Bits: 16/24
• Sampling Rate (per Second): 105
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 4.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7719EB - BOARD EVAL FOR AD7719
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7719
Pin No. Mnemonic
16
17
18
19
20
21
22
23
24
25
26
27
28
P2/SW2
PWRGND
P1/SW1
RESET
SCLK
CS
RDY
DOUT
DIN
DGND
DV
XTAL2
XTAL1
DD
Function
Dual-Purpose Pin. It can act as a general-purpose output (P2) bit referenced between AV
or as a low-side power switch (SW2) to PWRGND.
Ground Point for the Low-Side Power Switches SW2 and SW1. PWRGND must be tied to AGND.
Dual-Purpose Pin. It can act as a general-purpose output (P1) bit referenced between AV
or as a low-side power switch (SW1) to PWRGND.
Digital Input Used to Reset the ADC to Its Power-On Reset Status. This pin has a weak pull-up internally
to DV
Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input,
making the interface suitable for opto-isolated applications. The serial clock can be continuous with all
data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the
information being transmitted to or from the AD7719 in smaller batches of data. A weak pull-up to DV
is provided on the SCLK input.
Chip Select Input. This is an active low logic input used to select the AD7719. CS can be used to select
the AD7719 in systems with more than one device on the serial bus or as a frame synchronization signal in
communicating with the device. CS can be hardwired low, allowing the AD7719 to be operated in 3-wire
mode with SCLK, DIN, and DOUT used to interface with the device. A weak pull-up to DV
on the CS input.
RDY is a logic low status output from the AD7719. RDY is low if either the main ADC or auxiliary ADC
channel has valid data in its data register. This output returns high on completion of a read operation
from the data register. If data is not read, RDY will return high prior to the next update, indicating to the
user that a read operation should not be initiated. The RDY pin also returns low following the completion
of a calibration cycle. The RDY pin is effectively the digital NOR function of the RDY0 and RDY1 bits in
the Status register. If one of the ADCs is disabled, the RDY pin reflects the active ADC. RDY does not
return high after a calibration until the mode bits are written to, enabling a new conversion or calibration.
Since the RDY pin provides information on both the main and aux ADCs, when either the main or aux
ADC is disabled, it is recommended to immediately read its data register to ensure that its RDY bit goes
inactive and releases the RDY pin to indicate output data updates on the remaining active ADC.
Serial Data Output Accessing the Output Shift Register of the AD7719. The output shift register can
contain data from any of the on-chip data, calibration, or control registers.
Serial Data Input Accessing the Input Shift Register on the AD7719. Data in this shift register is transferred
to the calibration or control registers within the ADC depending on the selection bits of the Communications
register. A weak pull-up to DV
Ground Reference Point for the Digital Circuitry.
Digital Supply Voltage, 3 V or 5 V Nominal.
Output from the 32 kHz Crystal Oscillator Inverter.
Input to the 32 kHz Crystal Oscillator Inverter.
DD
.
PIN FUNCTION DESCRIPTIONS (continued)
DD
is provided on the DIN input.
–10–
DD
DD
DD
and AGND
and AGND
is provided
REV. A
DD