STA328 STMicroelectronics, STA328 Datasheet - Page 45
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STA328
Manufacturer Part Number
STA328
Description
DIG AUDIO SYSTEM, 2-CH, 36POWERSSOP
Manufacturer
STMicroelectronics
Datasheet
1.STA328.pdf
(57 pages)
Specifications of STA328
Svhc
No SVHC (15-Dec-2010)
Package / Case
PowerSO
Interface
I2C
No. Of Pins
36
Operating Temperature Range
-20°C To +125°C
Supply Voltage Max
36V
Supply Voltage Min
10V
Termination
RoHS Compliant
Interface Type
I2C
Rohs Compliant
Yes
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Company
Part Number
Manufacturer
Quantity
Price
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STA328
7
7.1
7.2
7.3
User programmable processing
EQ - biquad equation
The biquads use the equation that follows. This is diagrammed in
where Y[n] represents the output and X[n] represents the input. Multipliers are 28-bit signed
fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF
(0.9999998808).
Coefficients stored in the user defined coefficient RAM are referenced in the following
manner:
"
"
"
"
"
The x represents the channel and the y the biquad number. For example C3H41 is the b0/2
coefficient in the fourth biquad for channel 3
Figure 18. Biquad filter
Pre-scale
The pre-scale block which precedes the first biquad is used for attenuation when filters are
designed that boost frequencies above 0 dBFS. This is a single 28-bit signed multiplier, with
0x800000 = -1 and 0x7FFFFF = 0.9999998808. By default, all pre-scale factors are set to
0x7FFFFF.
Post-scale
The STA328 provides one additional multiplication after the last interpolation stage and
before the distortion compensation on each channel. This is a 24-bit signed fractional
multiplier. The scale factor for this multiplier is loaded into RAM using the same I
as the biquad coefficients and the mix. All channels can use the same settings as channel 1
by setting the post-scale link bit.
CxHy0 = b1/2
CxHy1 = b2
CxHy2 = -a1/2
CxHy3 = -a2
CxHy4 = b0/2
Y[n] = 2(b0/2)X[n] + 2(b1/2)X[n - 1] + b2X[n - 2] - 2(a1/2)Y[n - 1] - a2Y[n - 2]
Z
Z
-1
-1
= b0X[n] + b1X[n - 1] + b2X[n - 2] - a1Y[n - 1] - a2Y[n - 2]
b
b
0
1
/2
/2
b
2
2
2
+
+
+
2
User programmable processing
-a
2
-a
1
/2
Figure 18
Z
Z
-1
-1
below.
2
C registers
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