CDB5343 Cirrus Logic Inc, CDB5343 Datasheet - Page 15
![EvalBd 98dB 24-bit 96kHz Stereo ADC](/photos/9/10/91059/cdb5343_sml.jpg)
CDB5343
Manufacturer Part Number
CDB5343
Description
EvalBd 98dB 24-bit 96kHz Stereo ADC
Manufacturer
Cirrus Logic Inc
Specifications of CDB5343
Number Of Adc's
1
Number Of Bits
24
Sampling Rate (per Second)
108k
Data Interface
Serial
Inputs Per Adc
2 Single
Power (typ) @ Conditions
60mW @ 5 V
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
CS5343, CS5344
Description/function
Audio A/D
Operating Supply Voltage
5 V
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
CS5343
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
Other names
598-1156
DS687F3
4.2
4.3
4.4
SDATA
SDATA
LRCK
SCLK
LRCK
SCLK
Serial Audio Interface
The CS5343 output is serial data in I²S audio format and the CS5344 output is serial data in Left-Justified
audio format.
Figures 1
overview of serial audio interface formats, please refer to Cirrus Application Note AN282.
Digital Interface
VA supplies power to both the analog and digital sections of the ADC, and also powers the serial port. Con-
sequently, the digital interface logic level must equal VA to within the limits specified under
teristics” on page
Analog Connections
The analog modulator samples the input signal at half of the internal master clock rate, or 6.144 MHz when
MCLK = 12.288 MHz. The digital filter will reject signals within the stopband of the filter. However, there is
no rejection for input signals which are multiples of the input sampling frequency (n
n=0,1,2,... Refer to
ternal shunt capacitor and internal input impedance form a single-pole RC filter to provide the appropriate
filtering of noise at the modulator sampling frequency. Additionally, the 180 pF capacitor acts as a charge
source for the internal sampling circuits. Capacitors of NPO or other high-quality dielectric will produce the
best results while capacitors with a large voltage coefficient (such as general-purpose ceramics) can de-
grade signal linearity.
23 22
23 22
and
9
9
8
8
Figures 4
2
7
7
display more information on the required timing for the serial audio interface format. For an
6
6
9.
5
5
Figure 6
Left Channel
4
4
Left Channel
Figure 5. CS5344 Left-Justified Serial Audio Interface
and
3
3
Input
2
2
5
Figure 4. CS5343 I²S Serial Audio Interface
1
1
which shows the recommended topology of the analog input network. The ex-
Figure 6. CS5343/4 Analog Input Network
show the I²S and Left-Justified data relative to SCLK and LRCK. Additionally,
0
0
R1
R2
1 µF
180pF
C0G
4/2/08
23 22
23 22
Draft
9
9
8
8
7
7
CS5343/4
AIN
6
6
5
5
Right Channel
4
4
Right Channel
3
3
2
2
1
1
0
0
×
6.144 MHz), where
“Digital Charac-
CS5343/4
23 22
23 22
15