CS5501-BS Cirrus Logic Inc, CS5501-BS Datasheet - Page 17

• Manufacturer Part Number: CS5501-BS
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5501-BS

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 16 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 20-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

excellent differential linearity achieved by the
CS5501. The CS5501/CS5503 also have excellent
integral linearity, which is accomplished with a
well-designed charge-balance architecture. Each
device also achieves low input drift through the
use of chopper-stabilized techniques in its input
stage. To assure that the CS5501/CS5503 achieves
excellent performance over time and temperature,
it uses digital calibration techniques to minimize
offset and gain errors to typically within 1/2
LSB at 16 bits in the CS5501 and 4 LSB at 20
bits in the CS5503.
Converter Calibration
The CS5501/CS5503 offer both self-calibration
and system level calibration capability. To under-
stand the calibration features, a basic
comprehension of the internal workings of the
converter are helpful. As mentioned previously in
this data sheet, the converter consists of two sec-
tions. First is the analog modulator which is a
delta-sigma type charge-balance converter. This
is followed by a digital filter. The filter circuitry
is actually an arithmetic logic unit (ALU) whose
architecture and instructions execute the filter
function. The modulator (explained in more de-
tail in the applications note "Delta-Sigma
Conversion Technique Overview") uses the VREF
voltage connected to pin 10 to determine the mag-
nitude of the voltages used in its feedback DAC.
The modulator accepts an analog signal at its in-
put and produces a data stream of 1’s and 0’s as
its output. This data stream value can change
DS31F2
+1/2
-1/2
+1
-1
0
0
Figure 8. CS5501 Differential Nonlinearity Plot
Codes
32,768
(from 1 to 0 or vice versa) every 256 CLKIN cy-
cles. As the input voltage increases the ratio of
1’s to 0’s out of the modulator increases propor-
tionally. The 1’s density of the data stream out of
the modulator therefore provides a digital repre-
sentation of the analog input signal where the 1’s
density is defined as the ratio of the number of 1’s
to the number of 0’s out of the modulator for a
given period of time. The 1’s density output of the
modulator is also a function of the voltage on the
VREF pin. If the voltage on the VREF pin in-
creases in value (say, due to temperature drift), and
the analog input voltage into the modulator remains
constant, the 1’s density output of the modulator will
decrease (less 1’s will occur). The analog input into
the modulator which is necessary to produce a given
binary output code from the converter is ratiometric
to the voltage on the VREF pin. This means that if
VREF increases by one per cent, the analog signal
on AIN must also increase by one per cent to main-
tain the same binary output code from the converter.
For a complete calibration to occur, the calibration
microcontroller inside the device needs to record
the data stream 1’s density out of the modulator
for two different input conditions. First, a "zero
scale" point must be presented to the modulator.
Then a "full scale" point must be presented to the
modulator. In unipolar self-cal mode the zero
scale point is AGND and the full scale point is the
voltage on the VREF pin. The calibration micro-
controller then remembers the 1’s density out of
the modulator for each of these points and calcu-
lates a slope factor (LSB/ V). This slope factor
CS5501/CS5503
65,535
17