CS5501-BS Cirrus Logic Inc, CS5501-BS Datasheet - Page 25

• Manufacturer Part Number: CS5501-BS
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5501-BS

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 16 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 20-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

will have to be empirically tested to see if it meets
the system requirements. It is recommended that
any testing include input signals across the entire
input span of the converter as the signal level will
affect the amount of noise from the reference in-
put which is transferred to the output data.
Voltage Reference
The voltage reference applied to the VREF input
pin defines the analog input range of the
CS5501/CS5503. The preferred reference is 2.5V,
but the device can typically accept references
from 1V to 3V. Input signals which exceed 2.6V
(+ or -) can cause some linearity degradation. Fig-
ure 14 illustrates the voltage reference
connections to the CS5501/CS5503.
The circuitry inside the VREF pin is identical to
that as seen at the AIN pin. The sample capacitor
(see Figure 12) requires packets of charge from
the external reference just as the AIN pin does.
Therefore the same settling time requirements ap-
ply. Most reference IC’s can handle this dynamic
load requirement without inducing errors. They
exhibit sufficiently low output impedance and
wide enough bandwidth to settle to within the
necessary accuracy in the requisite 64 CLKIN cy-
cles.
Noise from the reference is filtered by the digital
filter, but the reference should be chosen to mini-
mize noise below 10 Hz. The CS5501/CS5503
typically exhibit 0.1 LSB rms and 1.6 LSB rms
noise respectively. This specification assumes a
clean reference voltage.
DS31F2
Figure 14. Voltage Reference Connections
For Example
LT1019 -2.5
+5V
2.5 V
Many monolithic
VA+
VREF
AGND
CS5501
CS5503
band-gap references are available which can sup-
ply 2.5 V for use with the CS5501/CS5503.
Many of these devices are not specified for noise,
especially in the 0.1 to 10 Hz bandwidth. Some
of these devices may exhibit noise characteristics
which degrade the performance of the
CS5501/CS5503.
Power Supplies And Grounding
The CS5501/CS5503 use the analog ground con-
nection, AGND, as a measurement reference
node. It carries no power supply current. The
AGND pin should be used as the reference node
for both the analog input signal and for the refer-
ence voltage which is input into the VREF pin.
The analog and digital supply inputs are pinned
out separately to minimize coupling between the
analog and digital sections of the chip. To
achieve maximum performance, all four supplies
for the CS5501/CS5503 should be decoupled to
their respective grounds using 0.1 F capacitors.
This is illustrated in the System Connection Dia-
gram, Figure 15, at the beginning of this data
sheet.
As CMOS devices, the CS5501/CS5503 require
that the positive analog supply voltage always be
greater than or equal to the positive digital supply
voltage. If the voltage on the positive digital sup-
ply should ever become greater than the voltage
on the positive analog supply, diode junctions in
the CMOS structure which are normally reverse-
biased will become forward-biased. This may
cause the part to draw high currents and experi-
ence permanent damage. The connections shown
in Figure 15 eliminate this possibility.
To ensure reliable operation, be certain that power
is applied to the part before signals at AIN, VREF,
or the logic input pins are present. If current is
supplied into any pin before the chip is powered-
up, latch up may result. As a system, it is
desirable to power the CS5501/CS5503, the volt-
CS5501/CS5503
25