CS8406-CZ Cirrus Logic Inc, CS8406-CZ Datasheet - Page 18

• Manufacturer Part Number: CS8406-CZ
• Description: Transceiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8406-CZ

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5V
• Program Memory Type: 1 V
• Transceiver Type: Digital Audio
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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•VLRCK is a virtual word clock, which may not exist, and is used to illustrate the CUV timing.
•VLRCK duty cycle is 50%.
•In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, VLRCK frequency = 2xAES3 frame rate.
•If the serial audio input port is on slave mode and TCBL is an output, then VLRCK = ILRCK if SILRPOL = 0
and VLRCK = ILRCK if SILRPOL =1.
•If the serial audio input port is in master mode and TCBL is an input, then VLRCK = ILRCK if SILRPOL = 0
and VLRCK = ILRCK if SILRPOL =1.
(In/Output)
VLRCK
(Output)
(Output)
TXP(N)
TXP(N)
(In/Output)
(Input)
(Input)
SDIN
TCBL
(Output)
VLRCK
TXP(N)
(Input)
V/C/U
(Input)
SDIN
TCBL
U
Tth
Z
Z
* Assume MMTLR = 0
* Assume MMTLR = 1
Tth
Z
Figure 8. AES3 Transmitter Timing for C, U, and V Pin Input Data
Data [4]
Data [4]
Data [0]
Tsetup
Data [1]*
Data [0]*
VCU[0]
Y
Data [5]
Thold
Data [5]
Data [1]
AES3 Transmitter in Stereo mode
AES3 Transmitter in Mono mode
U[0]
VCU[1]
Y
Y
X
Data [6]
Data [6]
Data [2]
Data [3]*
Data [2]*
VCU[2]
Y
Data [7]
Data [7]
Data [3]
Tsetup ≥ 7.5% AES3 frame time
Thold = 0
Tth > 3 OMCK clocks, if TCBL is Input
Tsetup ≥ 15% AES3 frame time
Thold = 0
Tth > 3 OMCK clocks, if TCBL is Input
U[2]
VCU[3]
X
X
X
Data [8]
Data [8]
Data [4]
Data [5]*
Data [4]*
VCU[4]
CS8406
DS580F1