CS8406-CZ Cirrus Logic Inc, CS8406-CZ Datasheet - Page 35

• Manufacturer Part Number: CS8406-CZ
• Description: Transceiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8406-CZ

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5V
• Program Memory Type: 1 V
• Transceiver Type: Digital Audio
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS580F1
APMS
HWCK0
HWCK1
TCBLD
TCBL
CEN
V
U
COPY/C
EMPH
AUDIO
ORIG
TEST
10
20
27
11
15
16
17
18
19
28
1
3
2
7
8
Serial Audio Data Port Master/Slave Select ( Input ) - APMS should be connected to VL to set serial
audio input port as a master or connected to GND to set the port as a slave.
OMCK Clock Ratio Select ( Input ) - Selects the ratio of OMCK to the input sample rate (Fs). A pull-up to
VL or pull-down to GND is required to set the appropriate mode. See Table 4 on page 33.
Transmit Channel Status Block Direction ( Input ) - Connect TCBLD to VL to set TCBL as an output.
Connect TCBLD to GND to set TCBL as an input.
Transmit Channel Status Block Start ( Input / Output ) - When operated as output, TCBL is high during
the first sub-frame of a transmitted channel status block, and low at all other times. When operated as
input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be
the start of a channel status block.
C Bit Enable ( Input ) - Determines how the channel status data bits are input. When CEN is low, hard-
ware mode A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected
channel status data. When CEN is high, hardware mode B is selected, where the COPY/C pin is used to
enter serial channel status data.
Validity Bit ( Input ) - In hardware modes A and B, the V pin input determines the state of the validity bit
in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.
User Data Bit ( Input ) - In hardware modes A and B, the U pin input determines the state of the user
data bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.
COPY Channel Status Bit/C Bit (Input) - In hardware mode A (CEN = 0), the COPY/C and ORIG pins
determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream,
see Table 2 on page 33. In hardware mode B, the COPY/C pin becomes the direct C bit input data pin,
which is sampled on both edges of LRCK.
Pre-Emphasis Indicator ( Input ) - In hardware mode A (CEN = 0), the EMPH pin low sets the 3 empha-
sis channel status bits to indicate 50/15 µs pre-emphasis of the transmitted audio data. If EMPH is high,
then the three EMPH channel status bits are set to 000, indicating no pre-emphasis.
Audio Channel Status Bit ( Input ) - In hardware mode A (CEN = 0), the AUDIO pin determines the state
of the audio/non audio Channel Status bit in the outgoing AES3 data stream.
ORIG Channel Status Bit Control ( Input ) - In hardware mode A (CEN = 0), the ORIG and COPY/C
pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data
stream, see Table 2 on page 33.
Test Pins - These pins are unused inputs. It is recommended that these pins be tied to a supply (VL or
GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left floating, how-
ever current consumption from VL will increase by 25 µA per TEST pin that is left floating.
CS8406
35