DSPIC30F1010-30I/MM Microchip Technology, DSPIC30F1010-30I/MM Datasheet - Page 18

• Manufacturer Part Number: DSPIC30F1010-30I/MM
• Description: 6KB, Flash, 256bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 QFN-S 6x6mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-30I/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 8-1:
DS70284C-page 18
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
Note 1:
Opcode
One row of code memory consists of thirty-two 24-bit words. Refer to
information.
SCHECK
READD
READP
Reserved
PROGD
PROGP
PROGC
ERASEB
ERASED
ERASEP
QBLANK
QVER
Mnemonic
PROGRAMMING EXECUTIVE COMMAND SET
(1)
(1)
Length
words)
(16-bit
N/A
19
51
1
4
4
4
2
3
3
3
1
Time Out
300 msec Query if the code memory is blank.
msec/row
msec/row
msec/row
msec/row
1 msec
5 msec
5 msec
5 msec
5 msec
1 msec
N/A
1
1
5
5
Sanity check.
This command is reserved. It will return a NACK.
Program one row of code memory at the specified address, then
Bulk Erase (entire program memory), or erase by segment.
Query the programming executive software version.
Read N 16-bit words of Configuration registers or device ID
starting from specified address.
Read N 24-bit instruction words of code memory starting from
specified address.
Not implemented.
verify.
Write byte or 16-bit word to specified Configuration register.
Not Implemented.
Erase rows of code memory from specified address.
Description
Table 5-2
© 2010 Microchip Technology Inc.
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