DSPIC30F3010-20E/SO Microchip Technology, DSPIC30F3010-20E/SO Datasheet - Page 134

• Manufacturer Part Number: DSPIC30F3010-20E/SO
• Description: IC,DSP,16-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010-20E/SO

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F3010/3011
19.8
The analog input model of the 10-bit ADC is shown in
Figure
function of the internal amplifier settling time, device
V
For the ADC to meet its specified accuracy, the Charge
Holding Capacitor (C
charge to the voltage level on the analog input pin. The
Source Impedance (R
(R
Impedance combine to directly affect the time required
to charge the capacitor, C
impedance of the analog sources must therefore be
small enough to fully charge the holding capacitor
within the chosen sample time. To minimize the effects
of pin leakage currents on the accuracy of the A/D
converter,
impedance, R
is selected (changed), this sampling function must be
completed prior to starting the conversion. The internal
holding capacitor will be in a discharged state prior to
each sample operation.
FIGURE 19-3:
DS70141F-page 134
DD
IC
) and the Internal Sampling Switch (R
and the holding capacitor charge time.
Note:
19-3. The total sampling time for the ADC is a
A/D Acquisition Requirements
the
S
, is 5 kΩ. After the analog input channel
C
PIN
Legend: C
maximum
VA
value depends on device package and is not tested. Effect of C
Rs
HOLD
S
ADC ANALOG INPUT MODEL
), the Interconnect Impedance
V
I
R
R
C
LEAKAGE
ANx
PIN
T
IC
SS
HOLD
) must be allowed to fully
C
PIN
recommended
HOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch Resistance
= Sample/Hold Capacitance (from DAC)
various junctions
. The combined
V
DD
V
V
T
T
source
= 0.6V
= 0.6V
SS
)
R
I
± 500 nA
LEAKAGE
IC
≤ 250Ω
The user must allow at least 1 T
time, T
sample to be acquired. This sample time may be
controlled manually in software by setting/clearing the
SAMP bit, or it may be automatically controlled by the
ADC. In an automatic configuration, the user must
allow enough time between conversion triggers so that
the minimum sample time can be satisfied. Refer to the
Section 23.0 “Electrical Characteristics”
sample time requirements.
SAMP
Sampling
Switch
R
SS
, between conversions to allow each
PIN
negligible if Rs ≤ 5 kΩ.
R
SS
V
SS
C
= DAC capacitance
= 4.4 pF
≤ 3 kΩ
HOLD
© 2010 Microchip Technology Inc.
AD
period of sampling
for T
AD
and