PIC16C717-I/SS Microchip Technology, PIC16C717-I/SS Datasheet - Page 175
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16C717-I/SS
Manufacturer Part Number
PIC16C717-I/SS
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F818-ISO.pdf
(6 pages)
2.PIC16C770-ISO.pdf
(220 pages)
3.PIC16C770-ISO.pdf
(6 pages)
4.PIC16C770-ISO.pdf
(8 pages)
Specifications of PIC16C717-I/SS
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
309-1016 - ADAPTER 20-SSOP TO 18-DIP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16C717I/SS
- PIC16F818-ISO PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16C770-ISO PDF datasheet #4
- Current page: 175 of 220
- Download datasheet (4Mb)
15.5
FIGURE 15-18:
TABLE 15-17: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
Param.
71A*
72A*
73A*
2002 Microchip Technology Inc.
No.
70*
71*
72*
73*
74*
75*
76*
78*
79*
80*
(CKP = 0)
(CKP = 1)
SDI
SS
SCK
SCK
SDO
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
Note: Refer to Figure 15-4 for load conditions.
and are not tested.
Master SSP SPI Mode Timing Waveforms and Requirements
TssL2scH,
TssL2scL
TscH
TscL
TdiV2scH,
TdiV2scL
T
TscH2diL,
TscL2diL
TdoR
TdoF
TscR
TscF
TscH2doV,
TscL2doV
B
Symbol
2
B
SPI MASTER MODE TIMING (CKE = 0)
Characteristic
SS to SCK or SCK input
SCK input high time
(Slave mode)
SCK input low time
(Slave mode)
Setup time of SDI data input to SCK edge
Last clock edge of Byte1 to the 1st clock
edge of Byte2
Hold time of SDI data input to SCK edge
SDO data output rise time PIC16CXXX
SDO data output fall time
SCK output rise time
(Master mode)
SCK output fall time (Master mode)
SDO data output valid
after SCK edge
70
80
71
73
MSb IN
MSb
74
72
75, 76
Continuous
Single Byte
Continuous
Single Byte
PIC16LCXXX
PIC16CXXX
PIC16LCXXX
PIC16CXXX
PIC16LCXXX
BIT6 - - - - - -1
BIT6 - - - -1
1.25T
1.25T
PIC16C717/770/771
1.5T
78
79
Min
100
100
T
CY
40
40
—
—
—
—
—
—
—
—
CY
CY
CY
+ 40
+ 30
+ 30
LSb
79
78
LSb IN
Typ† Max Units
10
20
10
10
20
10
—
—
—
—
—
—
—
—
—
—
100
—
—
—
—
—
—
—
—
25
45
25
25
45
25
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS41120B-page 173
Note 1
Note 1
Note 1
Conditions
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