PIC16C717-I/SS Microchip Technology, PIC16C717-I/SS Datasheet - Page 22
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16C717-I/SS
Manufacturer Part Number
PIC16C717-I/SS
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F818-ISO.pdf
(6 pages)
2.PIC16C770-ISO.pdf
(220 pages)
3.PIC16C770-ISO.pdf
(6 pages)
4.PIC16C770-ISO.pdf
(8 pages)
Specifications of PIC16C717-I/SS
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
309-1016 - ADAPTER 20-SSOP TO 18-DIP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16C717I/SS
- PIC16F818-ISO PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16C770-ISO PDF datasheet #4
- Current page: 22 of 220
- Download datasheet (4Mb)
PIC16C717/770/771
2.2.2.7
This register contains the SSP Bus Collision and low-
voltage detect interrupt flag bits.
REGISTER 2-7:
DS41120B-page 20
bit 7
bit 6-4
bit 3
bit 2-0
PIR2 REGISTER
PERIPHERAL INTERRUPT REGISTER 2 (PIR2: 0Dh)
bit 7
LVDIF: Low Voltage Detect Interrupt Flag bit
1 = The supply voltage has fallen below the specified LVD voltage (must be cleared in software)
0 = The supply voltage is greater than the specified LVD voltage
Unimplemented: Read as '0'
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred while the SSP module configured in I
0 = No bus collision occurred
Unimplemented: Read as '0'
Legend:
R = Readable bit
- n = Value at POR
R/W-0
LVDIF
transmitting (must be cleared in software)
U-0
—
U-0
—
W = Writable bit
’1’ = Bit is set
U-0
—
.
Note:
R/W-0
BCLIF
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0
—
2002 Microchip Technology Inc.
2
C Master was
x = Bit is unknown
U-0
—
U-0
—
bit 0
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