PIC16C745T-I/SO Microchip Technology, PIC16C745T-I/SO Datasheet - Page 46

• Manufacturer Part Number: PIC16C745T-I/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C745T-I/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SCI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.35 V ~ 5.25 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3 bit
• Operating Supply Voltage: 4.35 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16C745/765
7.1
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is F
(T1CON<2>) has no effect since the internal clock is
always in sync.
FIGURE 7-1:
DS41124C-page 46
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
Timer1 Operation in Timer Mode
INT
Set flag bit
TMR1IF on
Overflow
. The synchronize control bit T1SYNC
TIMER1 BLOCK DIAGRAM
TMR1H
T1OSC
TMR1
TMR1L
Oscillator
Enable
T1OSCEN
(1)
Preliminary
Internal
Clock
F
INT
TMR1ON
on/off
TMR1CS
1
0
7.2
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripple-counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The pres-
caler however will continue to increment.
T1CKPS<1:0>
T1SYNC
Prescaler
1, 2, 4, 8
Timer1 Operation in Synchronized
Counter Mode
0
1
2
Synchronized
clock input
2000 Microchip Technology Inc.
Synchronize
SLEEP input
det