PIC16C745/P Microchip Technology, PIC16C745/P Datasheet
PIC16C745/P
Related parts for PIC16C745/P
PIC16C745/P Summary of contents
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... Operating voltage range - 4.35 to 5.25V • High Sink/Source Current 25/25 mA • Wide temperature range - Industrial (- • Low-power consumption: - < TBD @ 5V, 6 MHz - < TBD typical standby current 1999 Microchip Technology Inc. PIC16C745/765 Pin Diagrams 28-Pin DIP, SOIC MCLR/V RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V ...
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... NC 32 RC0/T1OSO/T1CKI 31 OSC2/CLKOUT 30 OSC1/CLKIN RE2/CS/AN7 26 RE1/WR/AN6 25 RE0/RD/AN5 24 RA5/AN4 23 RA4/T0CKI PIC16C765 6 MHz or 24 MHz POR, BOR (PWRT, OST) 8K 256 (Ports channel x 8 bit Yes USB, USART/SCI Yes 1999 Microchip Technology Inc. ...
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... However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: • Fill out and mail in the reader response form in the back of this data sheet. • E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document. 1999 Microchip Technology Inc. PIC16C745/765 To Our Valued Customers Advanced Information DS41124A-page 3 ...
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... PIC16C745/765 NOTES: DS41124A-page 4 Advanced Information 1999 Microchip Technology Inc. ...
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... PLL. The SLEEP (power-down) feature provides a power-saving mode. The user can wake up the chip from SLEEP through several external and internal interrupts and resets. 1999 Microchip Technology Inc. PIC16C745/765 A highly reliable Watchdog Timer (WDT), with a dedi- cated on-chip RC oscillator, provides protection against software lock-up, and also provides one way of waking the device from SLEEP ...
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... PIC16C745/765 NOTES: DS41124A-page 6 Advanced Information 1999 Microchip Technology Inc. ...
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... EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before produc- tion shipments are available. Please contact your local Microchip Technology sales office for more details. 2.4 Serialized Quick-Turnaround Production (SQTP Microchip offers a unique programming service where a few user-defined locations in each device are pro- grammed with different serial numbers ...
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... PIC16C745/765 NOTES: DS41124A-page 8 Advanced Information 1999 Microchip Technology Inc. ...
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... This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16CXX simple yet efficient. In addition, the learning curve is reduced significantly. 1999 Microchip Technology Inc. PIC16C745/765 PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. ...
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... Dual Port RAM USB USART Advanced Information PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V REF RA4/T0CKI RA5/AN4 PORTB RB0/INT RB<7:1> PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC6/TX/CK RC7/RX/DT PORTD (2) RD3:0/PSP3:0 (2) RD4/PSP4 (2) RD5/PSP5 (2) RD6/PSP6 (2) RD7/PSP7 PORTE (2) RE0/AN5/RD (2) RE1/AN6/WR (2) RE2/AN7/CS V USB D- XCVR D+ 1999 Microchip Technology Inc. ...
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... CCP1 V V USB USB Legend open drain Schmitt Trigger Note 1: Weak pull-ups. PORT B pull-ups are byte wide programmable. 2: PIC16C765 only. 1999 Microchip Technology Inc. PIC16C745/765 Input Output Type Type ST — Master Clear Power — Programming Voltage Xtal — Crystal/Resonator ST — ...
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... A/D Input (2) ST CMOS Bi-directional I/O TTL — Parallel Slave Port data input (2) AN — A/D Input Power — Power Power — Ground Power — Analog Power Power — Analog Ground Advanced Information Description (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) 1999 Microchip Technology Inc. ...
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... Instruction @ address SUB_1 Note: All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 1999 Microchip Technology Inc. PIC16C745/765 3.2 Instruction Flow/Pipelining An “ ...
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... PIC16C745/765 NOTES: DS41124A-page 14 Advanced Information 1999 Microchip Technology Inc. ...
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... Page 0 Page 1 On-chip Program Memory Page 2 Page 3 1999 Microchip Technology Inc. PIC16C745/765 4.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). Bits RP1 and RP0 are the bank select bits. ...
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... UEIR 192h UEIE 193h USTAT 194h UCTRL 195h UADDR 196h 197h (1) USWSTAT UEP0 198h UEP1 199h UEP2 19Ah (1) 19Bh (1) 19Ch (1) 19Dh (1) 19Eh (1) 19Fh USB Dual Port 1A0h Memory 64 Bytes 1DFh 1E0h 1EFh accesses 1F0h 70h-7Fh 1FFh 1999 Microchip Technology Inc. ...
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... These registers can be addressed from either bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear. 1999 Microchip Technology Inc. The Special Function Registers can be classified into two sets (core and peripheral). Those registers associ- ated with the “ ...
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... TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 — — — — — — — — — — PCFG1 PCFG0 ---- -000 ---- -000 1999 Microchip Technology Inc. ...
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... Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: These registers can be addressed from either bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear. 1999 Microchip Technology Inc. PIC16C745/765 Bit 5 ...
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... USB_RST --00 0000 --00 0000 CRC5 PID_ERR 0000 0000 0000 0000 CRC5 PID_ERR 0000 0000 0000 0000 — — ---x xx-- ---u uu-- SUSPND — --x0 000- --xq qqq- ADDR1 ADDR0 -000 0000 -000 0000 SWSTAT1 SWSTAT0 0000 0000 0000 0000 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
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... Buffer Address Low 1B7h — Reserved 1B8h- 40 byte USB Buffer 1DFh Legend unknown unchanged value depends on condition unimplemented read as ’0’. Shaded locations are unimplemented, read as ‘0’. 1999 Microchip Technology Inc. PIC16C745/765 Bit 5 Bit 4 Bit 3 Bit 2 PID3 PID2 PID1 PID0 — ...
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... Note 1: The C and DC bits operate as borrow and digit borrow bits, respectively, in subtrac- tion. See the SUBLW and SUBWF instruc- tions for examples. R-1 R/W-x R/W-x R/W (1) C bit0 (1) Advanced Information R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset (1) 1999 Microchip Technology Inc. ...
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... Microchip Technology Inc. Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the watchdog timer. R/W-1 R/W-1 R/W-1 R/W-1 PSA PS2 PS1 PS0 bit0 ...
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... GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt R/W-0 R/W-0 R/W-0 R/W-x RBIE T0IF INTF RBIF bit0 Advanced Information . R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: PIC16C745 device does not have a parallel slave port implemented; always maintain this bit clear. 1999 Microchip Technology Inc. PIC16C745/765 Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt ...
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... GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 R/W-0 USBIF CCP1IF TMR2IF TMR1IF bit0 Advanced Information R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... Capture Mode TMR1 register capture occurred (must be cleared in software TMR1 register capture occurred Compare Mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM Mode Unused 1999 Microchip Technology Inc. PIC16C745/765 U-0 U-0 U-0 R/W-0 — — ...
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... BODEN bit in the configuration word). U-0 U-0 R/W-0 R/W-q — — POR BOR bit0 Advanced Information R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). 1999 Microchip Technology Inc. PIC16C745/765 Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. ...
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... FFh 17Fh 1FFh Bank 1 Bank 2 Bank 3 Advanced Information INDIRECT ADDRESSING 0x20 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR,F ;inc pointer FSR,4 ;all done? NEXT ;no clear next ;yes continue Indirect Addressing 7 FSR register 0 location select 1999 Microchip Technology Inc. ...
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... MOVWF ADCON1 ; as digital inputs MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6> are always ; read as ’0’. 1999 Microchip Technology Inc. PIC16C745/765 FIGURE 5-1: BLOCK DIAGRAM OF RA<3:0> AND RA5 PINS Data Bus D WR Port CK Data Latch D WR TRIS ...
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... Timer 0 Clock Input ST Bi-directional I/O AN — A/D Input Bit 4 Bit 3 Bit 2 Bit 1 RA4 RA3 RA2 RA1 — — — PCFG2 PCFG1 Advanced Information Description Value on: Value on all Bit 0 POR, other resets BOR RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 PCFG0 ---- -000 ---- -000 1999 Microchip Technology Inc. ...
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... Any read or write of PORTB. This will end the mismatch condition. b) Clear flag bit RBIF. 1999 Microchip Technology Inc. PIC16C745/765 A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. ...
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... Bit 1 RB6 RB5 RB4 RB3 RB2 RB1 T0CS T0SE PSA PS2 PS1 Advanced Information Description Value on: Value on all Bit 0 POR, other resets BOR RB0 uuuu uuuu xxxx xxxx 1111 1111 1111 1111 PS0 1111 1111 1111 1111 1999 Microchip Technology Inc. ...
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... BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. 1999 Microchip Technology Inc. PIC16C745/765 FIGURE 5-5: PORTC BLOCK DIAGRAM PORT/PERIPHERAL Select ...
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... USART Async Receive ST CMOS USART Data I/O Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 — — — RC2 RC1 — — — TRISC2 TRISC1 TRISC0 11-- -111 Advanced Information Description Value on: Value on all Bit 0 POR, other resets BOR RC0 xx-- -xxx uu-- -uuu 11-- -111 1999 Microchip Technology Inc. ...
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... Bit 6 08h (1) RD7 RD6 PORTD 88h (1) PORTD Data Direction Register TRISD Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by PORTD. Note 1: PIC16C765 only. 1999 Microchip Technology Inc. PIC16C745/765 FIGURE 5-6: PORTD BLOCK DIAGRAM Data Bus D WR PORT CK Data Latch D Q ...
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... Parallel Slave Port control input (1) AN — A/D Input ST CMOS Bi-directional I/O TTL — Parallel Slave Port data input (1) AN — A/D Input Advanced Information PORTE BLOCK DIAGRAM I/O pin Q Schmitt Trigger Input Buffer Description (1) (1) (1) (1) (1) (1) 1999 Microchip Technology Inc. ...
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... PORTE 89h (1) IBF OBF IBOV PSPMODE TRISE 9Fh ADCON1 — — — Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by PORTE. Note 1: PIC16C765 only. 1999 Microchip Technology Inc. PIC16C745/765 (1) (TRISE: 89h) U-0 R/W-1 R/W-1 R/W-1 — TRISE2 TRISE1 TRISE0 bit0 Bit 4 Bit 3 ...
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... PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Data Bus D WR PORT PCFG<2:0> PORT One bit of PORTD Set interrupt flag PSPIF (PIR1<7>) Advanced Information RDx pin TTL Read TTL RD Chip Select TTL CS Write TTL WR 1999 Microchip Technology Inc. ...
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... GIE PEIE T0IE Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745. Always maintain these bits clear. 2: PIC16C765 only. 1999 Microchip Technology Inc ...
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... PIC16C745/765 NOTES: DS41124A-page 42 Advanced Information 1999 Microchip Technology Inc. ...
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... X Watchdog Timer PSA WDT Enable bit Note: T0CS, T0SE, PSA, PS<2:0> are (OPTION_REG<5:0>). 1999 Microchip Technology Inc. PIC16C745/765 Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 (OPTION_REG< ...
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... Bit 3 Bit 2 Bit 1 T0IE INTE RBIE T0IF INTF T0CS T0SE PSA PS2 PS1 Advanced Information Value on: Value on all Bit 0 POR, other resets BOR xxxx xxxx uuuu uuuu RBIF 0000 000x 0000 000u PS0 1111 1111 1111 1111 1999 Microchip Technology Inc. ...
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... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: On the rising edge after the first falling edge. 1999 Microchip Technology Inc. PIC16C745/765 In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON< ...
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... The pres- caler however will continue to increment. 0 TMR1L 1 TMR1ON T1SYNC on/off 1 Prescaler T1OSCEN F INT Enable Internal 0 (1) Oscillator Clock 2 T1CKPS<1:0> TMR1CS Advanced Information Synchronized clock input Synchronize det SLEEP input 1999 Microchip Technology Inc. ...
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... It will continue to run during SLEEP primarily intended for use with a 32 kHz crystal. Table 7-1 shows the capacitor selection for the Timer1 oscillator. 1999 Microchip Technology Inc. PIC16C745/765 TABLE 7-1: CAPACITOR SELECTION FOR ...
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... CCP1IE TMR2IE Advanced Information Value on: Value on Bit 1 Bit 0 POR, all other BOR resets INTF RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1999 Microchip Technology Inc. ...
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... Timer2 is off bit 1-0: T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 1999 Microchip Technology Inc. PIC16C745/765 8.1 Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • ...
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... TXIE USBIE CCP1IE TMR2IE Advanced Information Value on: Value on Bit 0 POR, all other BOR resets 0000 000x 0000 000u RBIF 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 1999 Microchip Technology Inc. ...
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... The PWMs will have the same frequency and update rate (TMR2 interrupt). PWM Capture None. PWM Compare None. 1999 Microchip Technology Inc. PIC16C745/765 CCP2 Module: Capture/Compare/PWM Register1 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is gen- erated by a compare match and will reset Timer1 and start an A/D conversion (if the A/D module is enabled) ...
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... Compare mode, generate software interrupt on match (CCPnIF bit is set, CCPn pin is unaffected) 1011 = Compare mode, trigger special event (CCPnIF bit is set; CCPn resets TMR1or TMR3) 11xx = PWM mode DS41124A-page 52 R/W-0 R/W-0 R/W-0 R/W-0 CCPnM2 CCPnM1 CCPnM0 Advanced Information R = Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... Capture and Enable edge detect TMR1H CCP1CON<3:0> Q’s 1999 Microchip Technology Inc. PIC16C745/765 9.1.2 TIMER1 MODE SELECTION Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use the capture feature. In asynchronous counter mode, the capture operation may not work. ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as asserted high. from the Advanced Information SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> RC2/CCP1 (Note 1) S TRISC <2> Clear Timer, CCP1 pin and latch D.C. PWM OUTPUT Period (1) 1999 Microchip Technology Inc. ...
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... Resolution log(2) Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. 1999 Microchip Technology Inc. PIC16C745/765 9.3.3 SET-UP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1 ...
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... CCP2IF ---- ---0 ---- ---0 TMR1IE 0000 0000 0000 0000 — CCP2IE ---- ---0 ---- ---0 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1999 Microchip Technology Inc. ...
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... USB peri- odically polls these devices at a fixed rate to see if there is data to transfer. - Control Transfers are used for configuration purposes. 1999 Microchip Technology Inc. PIC16C745/765 10.1.2 FRAMES Information communicated on the bus is grouped in a format called Frames. Each Frame duration and is composed of multiple transfers ...
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... USTAT register, which gives the MCU the information it needs to process the endpoint. At this point the MCU will process the data and set the corre- sponding UOWN bit. Figure 10-1 shows a time line of how a typical USB token would be processed. Advanced Information 1999 Microchip Technology Inc. ...
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... FIGURE 10-1: USB TOKENS USB RESET USB_RST Interrupt Generated SETUP TOKEN IN TOKEN OUT TOKEN = Host = Device 1999 Microchip Technology Inc. PIC16C745/765 DATA DATA DATA Advanced Information ACK TOK_DNE Interrupt Generated ACK TOK_DNE Interrupt Generated ACK TOK_DNE Interrupt Generated DS41124A-page 59 ...
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... PIR1 (USBIF). Once an interrupt bit has been set, it must be cleared by writing a 0. R/C-0 R/C-0 R/C-0 R/C-0 UERR USB_RST Advanced Information R = Readable bit C = Clearable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... UERR: Set to enable ERROR interrupts ERROR interrupt enabled 0 = ERROR interrupt disabled bit 0: USB_RST: Set to enable USB_RST interrupts USB_RST interrupt enabled 0 = USB_RST interrupt disabled Note 1: This interrupt is the only interrupt active during UCTRL suspend = 1. 1999 Microchip Technology Inc. PIC16C745/765 R/W-0 R/W-0 R/W-0 R/W-0 TOK_DNE ACTIVITY UERR ...
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... Thus, the inter- rupt will typically not correspond with the end of a token being processed. R/C-0 R/C-0 R/C-0 R/C-0 DFN8 CRC16 CRC5 PID_ERR Advanced Information R/C Readable bit C = Clearable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... CRC16 interrupt enabled 0 = CRC16 interrupt disabled bit 1: CRC5: Set this bit to enable CRC5 interrupts CRC5 interrupt enabled 0 = CRC5 interrupt disabled bit 0: PID_ERR: Set this bit to enable PID_ERR interrupts PID_ERR interrupt enabled 0 = PID_ERR interrupt disabled 1999 Microchip Technology Inc. PIC16C745/765 R/W-0 R/W-0 R/W-0 R/W-0 DFN8 CRC16 CRC5 PID_ERR ...
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... STAT value. If the data in the STAT holding register is valid, the SIE will immedi- ately reassert the TOK_DNE interrupt. R-X R-X R-X U-0 ENDP1 ENDP0 IN — Advanced Information U-0 — Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset X = Don’t care 1999 Microchip Technology Inc. ...
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... UIDLE interrupt. It will generally be reset after an ACTIVITY interrupt. The V pin will still be driven, however the transceiver outputs are disabled. USB 1 = USB module in power conserve mode 0 = USB module normal operation bit 0: Unimplemented: Read as ’0’. 1999 Microchip Technology Inc. PIC16C745/765 R/W-0 R/W-0 R/W-0 U-0 — Advanced Information ...
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... DS41124A-page 66 R/W-0 R/W-0 R/W-0 R/W-0 ADDR3 ADDR2 ADDR1 ADDR0 R/W-0 R/W-0 R/W-0 R/W Configuration Status Buffer Advanced Information R = Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... Endpoint Enable register, but is only valid if EP_IN_EN=1 or EP_OUT_EN=1. Any access to this endpoint will cause the USB to return a STALL handshake. The EP_STALL bit can be set or cleared by the SIE. Refer to the USB 1.1 Specification, Sections 4.4.4 and 8.5.2 for more details on the STALL protocol. 1999 Microchip Technology Inc. PIC16C745/765 R/W-0 R/W-0 ...
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... Set the data 0/1 bit - Update the byte count - Clear the UOWN bit • The MCU is interrupted and reads the USTAT, translates that value to a BD, where the UOWN, PID, Data 0/1, and byte count values are checked. DS41124A-page 68 Advanced Information 1999 Microchip Technology Inc. ...
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... DATA0/1: This bit defines the type of data toggle packet that was transmitted or received Data 1 packet 0 = Data 0 packet bit 5-2: PID<3:0>: Packet Identifier. The received token PID value bit 1-0: Reserved: Read as 'X'. Note: Recommend that users not use BSF, BCF due to the dual functionality of this register. 1999 Microchip Technology Inc. PIC16C745/765 W-X W-X U-X U-X DTS BSTALL — ...
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... This drive USB current is sufficient for a pull-up only. 10.8 USB Software Libraries Microchip Technology provides a comprehensive set of Chapter 9 Standard requests functions to aid devel- opers in implementing their designs. See Microchip Technology’s website for the latest version of the soft- ware libraries. ...
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... USB Peripheral 10.9.2 INTEGRATING USB INTO YOUR APPLICATION The latest version of the USB interface software is available on Microchip Technology’s website. See http://www.microchip.com/ Communicating on USB is similar to communicating via a hardware USART. The main difference is that a USART typically works on a single byte at a time, where USB operates on a buffer bytes at a time ...
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... DEFAULT state. Now it can respond to commands on address zero. From there the rest of the enumeration process takes place, including assigning an address to the device through the SET_ADDRESS command and selecting a Advanced Information The device will immediately configuration through the 1999 Microchip Technology Inc. ...
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... No: try again until successful goto idleloop ; Yes: restart loop end 1999 Microchip Technology Inc. PIC16C745/765 CheckSleep is a separate call that takes the bus idle one step further and puts the device to sleep if the USB peripheral has detected no activity on the bus. ...
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... This define includes code to count the number of errors that occur, by type of error. This requires extra code and RAM locations to implement the counters. 10.9.7.3 #define FUNCTIONIDS This is useful for debug. It encodes the upper 6 bits of USWSTAT (0x197) to indicate which function is exe- cuting. DS41124A-page 74 Advanced Information 1999 Microchip Technology Inc. ...
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... TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0: TX9D: 9th bit of transmit data. (Can be used for parity.) 1999 Microchip Technology Inc. PIC16C745/765 as a half duplex synchronous system that can commu- nicate with peripheral devices, such as A/D or D/A inte- grated circuits, Serial EEPROMs etc. ...
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... Overrun error (Can be cleared by clearing bit CREN overrun error bit 0: RX9D: 9th bit of received data. (Can be used for parity.) DS41124A-page 76 U-0 R-0 R-0 R-x — FERR OERR RX9D Advanced Information R = Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC16C745/765 Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before output- ting the new baud rate. 11.1.1 ...
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... MHz Actual % of SPBRG Baud Error 77 38 9615.38 0.16 155 18 19230.77 0. 38461.54 0. 57692.31 0. 115384.62 0.16 12 250000.00 8.51 5 500000.00 8.51 2 Value on: Value on all Bit 0 POR, other resets BOR 0000 -010 0000 -010 0000 -00x 0000 -00x 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
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... Interrupt TXEN Baud Rate CLK SPBRG Baud Rate Generator 1999 Microchip Technology Inc. PIC16C745/765 ( PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in soft- ware. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicated the sta- tus of the TXREG register, another bit TRMT (TXSTA< ...
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... Transmit Shift Reg. Value on: Value on Bit 0 POR, all other BOR Resets TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
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... CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. 1999 Microchip Technology Inc. PIC16C745/765 two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register ...
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... Advanced Information Value on: Value on Bit 0 POR, all other BOR Resets TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
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... The DT and CK pins will revert to hi-imped- ance. If either bit CREN or bit SREN is set during a transmission, the transmission is aborted and the DT 1999 Microchip Technology Inc. PIC16C745/765 pin reverts to a hi-impedance state (for a reception). The CK pin will remain an output if bit CSRC is set (internal clock) ...
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... Resets BOR TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 bit 1 bit 7 WORD 2 ’1’ bit6 bit7 1999 Microchip Technology Inc. ...
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... Legend unknown unimplemented read as '0'. Shaded cells are not used for synchronous master reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear. 1999 Microchip Technology Inc. OERR set. The ninth receive bit is buffered the same way as the receive data ...
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... Note: Timing diagram demonstrates SYNC master mode with bit SREN = ’1’ and bit BRG = ’0’. DS41124A-page Q4Q1 Q4Q1 Q4Q1 bit1 bit2 bit3 bit4 bit5 Advanced Information bit6 bit7 ’0’ 1999 Microchip Technology Inc. ...
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... If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. 1999 Microchip Technology Inc. PIC16C745/765 11.4.2 USART SYNCHRONOUS SLAVE RECEPTION The operation of the synchronous master and slave modes is identical, except in the case of the SLEEP mode. Also, bit SREN is a don’ ...
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... Value on: Value on all Bit 0 POR, other Resets BOR TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
Page 89
... ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current Note 1: A/D channels 5, 6 and 7 are implemented on the PIC16C765 only. 1999 Microchip Technology Inc. PIC16C745/765 The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived from the A/D’ ...
Page 90
... REF REF Advanced Information R = Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset V REF V DD RA3 V DD AN3 V DD AN3 V DD 1999 Microchip Technology Inc. ...
Page 91
... Wait the required acquisition time. FIGURE 12-1: A/D BLOCK DIAGRAM A/D Converter V REF (Reference voltage) Note 1: Not available on PIC16C745. 1999 Microchip Technology Inc. PIC16C745/765 4. Start conversion: • Set GO/DONE bit (ADCON0) 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • ...
Page 92
... V DD Sampling Switch leakage = 0. ± 500 In(1/511) S Advanced Information the minimum acquisition time, , see ACQ ACQ SS C HOLD = DAC capacitance = 51 Sampling Switch (k ) 1999 Microchip Technology Inc. ...
Page 93
... Analog levels on any pin that is defined as a digital input, but not as an analog input, may cause the input buffer to consume current that is out of specification. 3: The TRISE register is not provided on the PIC16C745. 1999 Microchip Technology Inc. PIC16C745/765 . The AD are: AD time ...
Page 94
... TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu — ADON 0000 00-0 0000 00-0 PCFG1 PCFG0 ---- -000 ---- -000 --0x 0000 --0u 0000 RA1 RA0 --11 1111 --11 1111 (1) (1) ---- -xxx ---- -uuu RE1 RE0 0000 -111 0000 -111 Data Direction Bits 1999 Microchip Technology Inc. ...
Page 95
... E4- External clock with 4x PLL enabled. CLKOUT on OSC2 pin Note 1: All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed. 1999 Microchip Technology Inc. PIC16C745/765 keep the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which pro- ...
Page 96
... In H4 mode, a PLL module is switched on in-line with the clock provided across OSC1 and OCS2. The output of the PLL drives F Advanced Information CERAMIC RESONATORS Freq OSC1 OSC2 TBD TBD CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Cap. Range Cap. Range Freq C1 C2 TBD TBD . INT 1999 Microchip Technology Inc. ...
Page 97
... PD bits are set or cleared differently in different reset situations as indicated in Table 13-4. These bits are used in software to determine the nature of the reset. See Table 13-7 for a full description of reset states of all registers. 1999 Microchip Technology Inc. PIC16C745/765 13.2.5 E4 MODE In E4 mode, a PLL module is switched on in-line with the clock provided to OSC1 ...
Page 98
... Reset MCLR SLEEP WDT Time-out Module Reset Power-on Reset V rise DD detect V DD Brown-out Reset OST/PWRT OST 10-bit Ripple counter OSC1 PWRT Dedicated 10-bit Ripple counter On-chip RC OSC DS41124A-page 98 Enable PWRT Enable OST Advanced Information S Chip Reset R Q 1999 Microchip Technology Inc. ...
Page 99
... OSC1 input) after the PWRT delay. This ensures that the crystal oscillator or resona- tor has started and stabilized. The OST time-out is invoked only for HS mode and only on power-on reset or wake-up from SLEEP. 1999 Microchip Technology Inc. PIC16C745/765 13.4.4 BROWN-OUT RESET (BOR ...
Page 100
... SLEEP PWRTE = 1 1024 T 1024 T OSC OSC T + 1024 PLLRT OSC PLLRT 1024 T OSC PLLRT PLLRT PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu Value on: Value on all Bit 0 POR, BOR other resets C 0001 1xxx 000q quuu BOR ---- --qq ---- --uu 1999 Microchip Technology Inc. ...
Page 101
... Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 13-5 for reset value for specific condition. 4: PIC16C765 only. 1999 Microchip Technology Inc. PIC16C745/765 MCLR Resets WDT Reset ...
Page 102
... Advanced Information Wake-up via WDT or Interrupt uuuu -uuu uuuu uuuu ---- ---u ---- --uu 1111 1111 uuuu -uuu uuuu uuuu ---- -uuu --00 0000 --00 0000 0000 0000 0000 0000 ---u uu-- --xq qqq- -000 0000 0000 0000 ---- 0000 ---- 0000 ---- 0000 1999 Microchip Technology Inc. ...
Page 103
... The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 1999 Microchip Technology Inc. PIC16C745/765 Note interrupt occurs while the Global ...
Page 104
... TXIF USBIF CCP1IF Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Advanced Information (2) 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) Wake-up (If in SLEEP mode) Interrupt to CPU TMR2IF TMR1IF CCP2IF Yes Yes Yes Yes Yes Yes 1999 Microchip Technology Inc. ...
Page 105
... W_TEMP,F ; SWAPF W_TEMP,W ; swapf loads W without affecting STATUS flags RETFIE 1999 Microchip Technology Inc. PIC16C745/765 13.7 Context Saving During Interrupts During an interrupt, only the PC is saved on the stack. At the very least, W and STATUS should be saved to preserve the context for the interrupted program. All registers that may be corrupted by the ISR, such as PCLATH or FSR, should be saved ...
Page 106
... PWRTE WDTE T0CS T0SE PSA PS2 Advanced Information can be realized. WDT = Min., Temperature = Max., and DD PS<2:0> To TMR0 MUX (Figure 6-1) PSA Value on Value on Bit 1 Bit 0 All Other POR, BOR Resets PLL FOSC0 PS1 PS0 1111 1111 1111 1111 1999 Microchip Technology Inc. ...
Page 107
... A/D conversion (when A/D clock source is dedi- cated internal oscillator). 6. USART (synchronous slave mode). 1999 Microchip Technology Inc. PIC16C745/765 Other peripherals cannot generate interrupts since dur- ing SLEEP, no on-chip Q clocks are present. When the SLEEP instruction is being executed, the next instruction ( pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...
Page 108
... FIGURE 13-9: TYPICAL IN-CIRCUIT SERIAL External Connector Signals + CLK Data I/O Advanced Information (2) 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h (see programming IL IHH PROGRAMMING CONNECTION To Normal Connections PIC16CXX MCLR/V PP RB6 RB7 Normal Connections 1999 Microchip Technology Inc. ...
Page 109
... Assigned to < > Register bit field In the set of i talics User defined term (font is courier) 1999 Microchip Technology Inc. PIC16C745/765 The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations ...
Page 110
... C,DC,Z kkkk kkkk Z kkkk kkkk kkkk kkkk PD TO 0110 0100 , kkkk kkkk Z kkkk kkkk kkkk kkkk 0000 1001 kkkk kkkk 0000 1000 TO PD 0110 0011 , C,DC,Z kkkk kkkk Z kkkk kkkk Mid-Range MCU Family ™ 1999 Microchip Technology Inc. ...
Page 111
... Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND’ed with the eight bit literal 'k'. The result is placed in the W register 1999 Microchip Technology Inc. PIC16C745/765 ANDWF Syntax: Operands: Operation: Status Affected: Description: . BCF Syntax: Operands: Operation: ...
Page 112
... Z W register is cleared. Zero bit (Z) is set. Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. 1999 Microchip Technology Inc. ...
Page 113
... W register. If ’d’ the result is placed back in reg- ister ’f’. If the result is 1, the next instruc- tion is executed. If the result is 0, then a NOP is executed instead making instruction. CY 1999 Microchip Technology Inc. PIC16C745/765 GOTO Syntax: Operands: Operation: Status Affected: Description: INCF ...
Page 114
... The eight bit literal 'k' is loaded into W . register The don’t cares will assem- ble as 0’s. Move label ] MOVWF 127 (W) (f) None Move data from W register to reg- ister ’f’. No Operation [ label ] NOP None No operation None No operation. 1999 Microchip Technology Inc. ...
Page 115
... TOS PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction. 1999 Microchip Technology Inc. PIC16C745/765 RLF Syntax: Operands: Operation: Status Affected: Description: RRF Syntax: ...
Page 116
... The result is placed in the W register. Exclusive OR W with f [ label ] XORWF f 127 d [0,1] (W) .XOR. (f) destination) Z Exclusive OR the contents of the W register with register 'f the result is stored in the W register the result is stored back in register 'f'. 1999 Microchip Technology Inc. ...
Page 117
... A full featured editor • A project manager • Customizable tool bar and key mapping • A status bar • On-line help 1999 Microchip Technology Inc. PIC16C745/765 MPLAB allows you to: • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download ...
Page 118
... PICmicro MCU. 15.7 PICMASTER/PICMASTER CE The PICMASTER system from Microchip Technology is a full-featured, professional quality emulator system. This flexible in-circuit emulator provides a high-quality, universal platform for emulating Microchip 8-bit PICmicro microcontrollers (MCUs). PICMASTER sys- tems are sold worldwide, with a CE compliant model available for European Union (EU) countries ...
Page 119
... SIMICE is an entry-level hardware development sys- tem designed to operate in a PC-based environment with Microchip’s simulator MPLAB-SIM. Both SIMICE and MPLAB-SIM run under Microchip Technology’s MPLAB Integrated Development Environment (IDE) software. Specifically, SIMICE provides hardware sim- ulation for Microchip’s PIC12C5XX, PIC12CE5XX, and PIC16C5X families of PICmicro 8-bit microcontrollers ...
Page 120
... EE OQ Microchips HCS Secure Data Products. The HCS eval- uation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters. DS41124A-page 120 PIC17C756, Advanced Information 1999 Microchip Technology Inc. ...
Page 121
... PIC16C6X á á á á PIC16C5X á á á á PIC14000 á á á á PIC12CXXX Tools Software Emulators 1999 Microchip Technology Inc. á á á á á á á á á á á á á á á á á á ...
Page 122
... PIC16C745/765 NOTES: DS41124A-page 122 Advanced Information 1999 Microchip Technology Inc. ...
Page 123
... Exposure to maximum rating conditions for extended periods may affect device reliability. 1999 Microchip Technology Inc. (except V , MCLR and RA4)........................................... -0. ...
Page 124
... PIC16C745/765 FIGURE 16-1: VALID OPERATING REGIONS. FREQUENCY ON F -40°C TA +85°C 5.5 V 5.25 V 4.35 V 4.0 V DS41124A-page 124 . INT Frequency Advanced Information 24 MHz 1999 Microchip Technology Inc. ...
Page 125
... The current is the additional current consumed when this peripheral is enabled. This current should be added to the base measurement Module differential currents measured at F 1999 Microchip Technology Inc. PIC16C745/765 Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C -40°C Min Typ† ...
Page 126
... Conditions V V For entire V range Note For entire V range Note PIN DD Pin at hi-impedance PIN PIN DD HS osc mode 5V PIN 1999 Microchip Technology Inc. ...
Page 127
... In EC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. 2: The leakage current on the MCLR/V sent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 1999 Microchip Technology Inc. PIC16C745/765 Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C -40°C ...
Page 128
... CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings Fall H High I Invalid (Hi-impedance) L Low DS41124A-page 128 T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z Hi-impedance Advanced Information 1999 Microchip Technology Inc. ...
Page 129
... Operating temperature AC CHARACTERISTICS Operating voltage V Section 16.2. LC parts operate for commercial/industrial temperatures only. FIGURE 16-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 V Pin Note 1: PIC16C765 only. 1999 Microchip Technology Inc. 0°C T +70°C for commercial A -40°C T +85°C for industrial A range as described in DC spec Section 16 ...
Page 130
... OSC mode, PLL disabled OSC1 in EC mode with PLL disabled. INT DS41124A-page 130 equals F or CLKIN if the PLL is disabled. F INT OSC is always 4/F CY Advanced Information INT . F is OSC1 pin in EC INT INT 1999 Microchip Technology Inc. ...
Page 131
... All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. 1999 Microchip Technology Inc. PIC16C745/765 Min Typ† ...
Page 132
... CY T — OSC Advanced Information new value Units Conditions 200 ns Note 1 200 ns Note 1 100 ns Note 1 100 ns Note 1 0 Note 1 CY — ns Note 1 — ns Note 1 150 ns — ns — ns — — ns — ns 1999 Microchip Technology Inc. ...
Page 133
... T Brown-out Reset Pulse Width BOR * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 1999 Microchip Technology Inc. PIC16C745/765 ...
Page 134
... Must also meet parameter 47 — — ns — — ns — — ns — — ns — — prescale value ( prescale value ( — — ns — — ns — 200 kHz — 7Tosc — 1999 Microchip Technology Inc. ...
Page 135
... F CCP1 and CCP2 output fall time CC * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 1999 Microchip Technology Inc. PIC16C745/765 50 51 ...
Page 136
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41124A-page 136 65 Min Typ† 20 — 20 — 35 — — — 10 — Advanced Information 62 63 Max Units Conditions — ns — ns — 1999 Microchip Technology Inc. ...
Page 137
... Data hold after CK CK DTL *These parameters are characterized but not tested. †Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 1999 Microchip Technology Inc. PIC16C745/765 121 122 Min Typ† ...
Page 138
... REF AIN REF — AIN REF Average current consump- tion when A/D is on. (Note During V acquisition. AIN Based on differential charge HOLD AIN C , see Section 12.1. HOLD During A/D Conversion cycle A 1999 Microchip Technology Inc. ...
Page 139
... Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following T 2: See Section 12.1 for min conditions. 1999 Microchip Technology Inc. PIC16C745/765 131 130 ...
Page 140
... GND, cable shield or any other signal. BUS 90% 90 Min T † Max Units Conditions YP 75 300 ns 75 300 ns 1.3 2 125 % 0.8 V 2.0 V 2.7 3.6 V 0.2 V (D+)-(D-) 0.8 2.5 V 0.0 0.3 V 2.8 3.6 V 2.7 3.6 V Advanced Information 66.7ns 6MHz 4ns min 20ns max 10% 1999 Microchip Technology Inc. ...
Page 141
... DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and Tables not available at this time. 1999 Microchip Technology Inc. PIC16C745/765 Advanced Information DS41124A-page 141 ...
Page 142
... PIC16C745/765 NOTES: DS41124A-page 142 Advanced Information 1999 Microchip Technology Inc. ...
Page 143
... Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 1999 Microchip Technology Inc. PIC16C745/765 Example ...
Page 144
... PIC16C745/765 Package Marking Information (Cont’d) 40-Lead PDIP MMMMMMMMMMMMMM XXXXXXXXXXXXXXXXXX YYMMNNN 44-Lead TQFP MMMMMMMM XXXXXXXXXX XXXXXXXXXX YYMMNNN 44-Lead PLCC MMMMMMMM XXXXXXXXXX XXXXXXXXXX YYMMNNN DS41124A-page 144 Example PIC16C765/P 9917017 Example PIC16C765/PT 9917017 Example PIC16C765/L 9917017 Advanced Information 1999 Microchip Technology Inc. ...
Page 145
... Mold Draft Angle Top Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 1999 Microchip Technology Inc Units INCHES* MIN ...
Page 146
... E1 .288 .295 .299 D .695 .704 .712 h .010 .020 .029 L .016 .033 .050 .009 .011 .013 B .014 .017 .020 Advanced Information A2 MILLIMETERS MIN NOM MAX 28 1.27 2.36 2.50 2.64 2.24 2.31 2.39 0.10 0.20 0.30 10.01 10.34 10.67 7.32 7.49 7.59 17.65 17.87 18.08 0.25 0.50 0.74 0.41 0.84 1. 0.23 0.28 0.33 0.36 0.42 0. 1999 Microchip Technology Inc. ...
Page 147
... Shoulder to Shoulder Width Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Window Diameter *Controlling Parameter JEDEC Equivalent: MO-103 Drawing No. C04-013 1999 Microchip Technology Inc Units INCHES* MIN ...
Page 148
... E1 .530 .545 .560 D 2.045 2.058 2.065 L .120 .130 .135 c .008 .012 .015 B1 .030 .050 .070 B .014 .018 .022 eB .620 .650 .680 Advanced Information MILLIMETERS MIN NOM MAX 40 2.54 4.06 4.45 4.83 3.56 3.81 4.06 0.38 15.11 15.24 15.88 13.46 13.84 14.22 51.94 52.26 52.45 3.05 3.30 3.43 0.20 0.29 0.38 0.76 1.27 1.78 0.36 0.46 0.56 15.75 16.51 17. 1999 Microchip Technology Inc. ...
Page 149
... Mold Draft Angle Top Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-076 1999 Microchip Technology Inc. PIC16C745/765 ...
Page 150
... E1 .650 .653 .656 D1 .650 .653 .656 E2 .590 .620 .630 D2 .590 .620 .630 c .008 .011 .013 B1 .026 .029 .032 B .013 .020 .021 Advanced Information MILLIMETERS MIN NOM MAX 44 1.27 11 4.19 4.39 4.57 3.68 3.87 4.06 0.51 0.71 0.89 0.61 0.74 0.86 1.02 1.14 1.27 0.00 0.13 0.25 17.40 17.53 17.65 17.40 17.53 17.65 16.51 16.59 16.66 16.51 16.59 16.66 14.99 15.75 16.00 14.99 15.75 16.00 0.20 0.27 0.33 0.66 0.74 0.81 0.33 0.51 0. 1999 Microchip Technology Inc. ...
Page 151
... RB Port Pins .............................................................. 33 Timer0/WDT Prescaler .............................................. 43 Timer2 ....................................................................... 49 USART Receive ........................................................ 81 USART Transmit ....................................................... 79 Watchdog Timer ...................................................... 106 BOR bit .............................................................................. 99 BRGH bit ........................................................................... 77 Brown-out Reset (BOR) Timing Diagram ....................................................... 133 Buffer Descriptor Table ...................................................... 68 1999 Microchip Technology Inc. PIC16C745/765 C C bit ................................................................................... 22 Capture/Compare/PWM Capture Block Diagram ................................................... 53 CCP1CON Register .......................................... 52 CCP1IF ............................................................. 53 Mode ................................................................. 53 Prescaler ........................................................... 53 CCP Timer Resources ...
Page 152
... Power-Up-Timer (PWRT) .......................................... 99 TO ............................................................................. 97 POR bit .............................................................................. 99 Port RB Interrupt ............................................................. 105 , 103 PORTA ..................................................................... 20 PORTA Register ......................................................... 17 PORTB ..................................................................... 20 PORTB Register ......................................................... 17 PORTC ..................................................................... 20 PORTC Register ........................................................ 17 PORTD ..................................................................... 20 PORTD Register ........................................................ 17 PORTE ..................................................................... 20 Advanced Information , 100 , 100 , 101 , 101 , 31 , 101 , 33 , 101 , 35 , 101 , 37 , 101 1999 Microchip Technology Inc. ...
Page 153
... Special Features of the CPU ............................................. 95 Special Function Registers ................................................ 17 PIC16C745/765 ......................................................... 17 SPEN bit ............................................................................ 76 SREN bit ............................................................................ 76 SSPBUF ............................................................................ 19 Stack .................................................................................. 29 Overflows .................................................................. 29 Underflow .................................................................. 29 Status ................................................................................ 64 STATUS Register ..................................................... 22 Synchronous Serial Port Module ....................................... 57 1999 Microchip Technology Inc. PIC16C745/765 , T 38 T1CKPS0 bit ..................................................................... 45 T1CKPS1 bit ..................................................................... 45 T1CON .............................................................................. T1CON Register ......................................................... 19 T1OSCEN bit .................................................................... 45 T1SYNC bit ....................................................................... 45 T2CKPS0 bit ...
Page 154
... Wake-up from SLEEP ..................................................... 107 Watchdog Timer (WDT) ............................ 95 Timing Diagram ....................................................... 133 WDT ................................................................................ 100 Block Diagram ......................................................... 106 Period ...................................................................... 106 Programming Considerations .................................. 106 Timeout .................................................................... 101 WR pin ............................................................................... 40 WWW, On-Line Support ...................................................... bit .................................................................................... 22 DS41124A-page 154 , 100 106 Advanced Information 1999 Microchip Technology Inc. ...
Page 155
... Trademarks: The Microchip name, logo, PIC, PICmicro, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Flex ROM, MPLAB and fuzzy- LAB are trademarks and SQTP is a service mark of Microchip in the U ...
Page 156
... Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS41124A-page 156 Total Pages Sent FAX: (______) _________ - _________ N Literature Number: DS41124A Advanced Information 1999 Microchip Technology Inc. ...
Page 157
... Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 1999 Microchip Technology Inc. XXX Examples: Pattern a) PIC16C745/P 301 = Commercial temp., PDIP package, 6 MHz, QTP pattern #301. (2) ( (Commercial) Note 1: (Industrial) ...
Page 158
... Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip ...