PIC16C745/P Microchip Technology, PIC16C745/P Datasheet - Page 13

• Manufacturer Part Number: PIC16C745/P
• Description: 8-Bit CMOS Microcontrollers with USB
• Manufacturer: Microchip Technology

3.1
The clock input feeds an on-chip PLL. The clock output
from the PLL (F
erate four non-overlapping quadrature clocks namely,
Q1, Q2, Q3 and Q4. Internally, the program counter
(PC) is incremented every Q1, the instruction is fetched
from the program memory and latched into the instruc-
tion register in Q4. The instruction is decoded and exe-
cuted during the following Q1 through Q4. The clocks
and instruction execution flow is shown in Figure 3-2.
FIGURE 3-2:
EXAMPLE 3-1:
1. MOVLW 55h
2. MOVWF PORTB
3. CALL
4. BSF
5. Instruction @ address SUB_1
1999 Microchip Technology Inc.
Note:
OSC2/CLKOUT
Clocking Scheme/Instruction Cycle
(EC mode)
SUB_1
PORTA, BIT3 (Forced NOP)
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch
instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
F
INT
PC
INT
Q1
Q2
Q3
Q4
CLOCK/INSTRUCTION CYCLE
) is internally divided by four to gen-
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC-1)
Fetch INST (PC)
Q2
Fetch 1
T
PC
CY
0
Q3
Advanced Information
Q4
Execute 1
Fetch 2
T
CY
1
Q1
Execute INST (PC)
Fetch INST (PC+1)
Execute 2
Q2
Fetch 3
T
PC+1
CY
3.2
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
2
Q3
Execute 3
Q4
Fetch 4
Instruction Flow/Pipelining
T
CY
3
Q1
PIC16C745/765
Execute INST (PC+1)
Fetch INST (PC+2)
Fetch SUB_1 Execute SUB_1
Q2
Flush
T
PC+2
CY
4
Q3
Q4
DS41124A-page 13
T
CY
Internal
phase
clock
5