PIC16F677T-E/SS Microchip Technology, PIC16F677T-E/SS Datasheet - Page 64

• Manufacturer Part Number: PIC16F677T-E/SS
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F677T-E/SS

• Rohs Compliant: YES
• Mfg Application Notes: Intro to Capacitive Sensing Appl Notes Layout and Physical Design Appl Note
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 18
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPDM164125 - BOARD DEMO PICDEM TOUCH SENSE 1AC162061 - HEADER INTRFC MPLAB ICD2 20PIN
• Lead Free Status / Rohs Status: Details

PIC16F631/677/685/687/689/690
REGISTER 4-5:
REGISTER 4-6:
DS41262E-page 62
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
bit 3
bit 2-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-0
Note 1:
U-0
U-0
—
—
2:
3:
4:
2:
Global RABPU bit of the OPTION register must be enabled for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0).
The RA3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word.
WPUA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.
IOCA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
Unimplemented: Read as ‘0’
WPUA<5:4>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Unimplemented: Read as ‘0’
WPUA<2:0>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Unimplemented: Read as ‘0’
IOCA<5:0>: Interrupt-on-change PORTA Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
U-0
U-0
—
—
WPUA: PORTA REGISTER
IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
WPUA5
IOCA5
R/W-1
R/W-0
WPUA4
IOCA4
R/W-1
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
IOCA3
R/W-0
U-0
—
WPUA2
IOCA2
R/W-1
R/W-0
© 2008 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
WPUA1
IOCA1
R/W-1
R/W-0
WPUA0
IOCA0
R/W-1
R/W-0
bit 0
bit 0